Papers - IMAI Masashi
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A Process-variation-aware low-power technique using current control
VLD2007 ( 76 ) 37 - 42 2007.11
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A Method of Priority and Voltage/Frequency Control for Low-Power in Chip Multiprocessors
ARC-175 83 - 88 2007.11
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A Plan of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs
ARC-173 79 - 84 2007.5
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Design Method of High Performance and Low Power Functional Units Considering Delay Variations
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
IEICE Trans on Fundamentals E89-A ( 12 ) 3519 - 3528 2006.12
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A Novel Checkpointing for Cluster System with Non-uniform Failure-Rate
J89-D ( 8 ) 1705 - 1716 2006.8
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Overhead-Conscious Task Scheduling Scheme for Reducing Energy Consumption of Multi-Processor System-on-Chip
ARC-169 67 - 72 2006.8
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Low Power Delay-Insensitive Asynchronous Circuits using 1-out-of-4 Encoding
ICD2006 ( 82 ) 19 - 24 2006.8
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A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations
Masashi Imai, Takashi Nanya
Proc. Async2006 68 - 77 2006.3
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遅延変動特性を考慮したタイミング信号設計方式に関する検討
今井 雅,渡邊孝一,近藤正章,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2005 ( 59 ) 31 - 36 2005.11
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Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
VLD2005 ( 60 ) 37 - 42 2005.11
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Task and Voltage Scheduling for Reducing Energy Consumption on GALS System-on-Chip
ARC-164 61 - 66 2005.8
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Initial Discussion about Adaptive Checkpointing for HPC Cluster in View of Fluctuate of Failure-Rate
DC2005 ( 14 ) 7 - 12 2005.8
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Single Latched Scan Registers based on Multi-Clock for Low Heat Dissipation and for Low IR-Drop
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
Proc. ITC-CSCC2005 945 - 946 2005.7
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A Novel Design Method using Delay-Variation-Aware Cell Libraries for Asynchronous Bundled-data Transfer Circuits
Masashi Imai, Chikaaki Kogure, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Proc. ITC-CSCC2005 441 - 442 2005.7
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A Design Method for a Standard Cell Library Considering Delay Variation
VLD2004 ( 63 ) 13 - 18 2004.12
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Skewed Checkpointing for Tolerating Multi-Node Failures
Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
Proc. SRDS2004 116 - 125 2004.10
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Asynchronous scan-latch controller for low area overhead DFT
M.Tsukisaka, M.Imai, T.Nanya
Proc. ICCD2004 66 - 71 2004.10
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A Synthesis Method of Asynchronous Control Circuits from a Behaviroal Description
289 - 294 2004.7
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Skewed Checkpointing for Tolerating Multi-Node Failures in Cluster System
DC2004 ( 19 ) 37 - 42 2004.7
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Design Space Reduction Filter in Asynchronous Data-path Synthesis
295 - 300 2004.7