Papers - IMAI Masashi
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Development of Quantum Annealing Simulator with Input Signal Uncertainties
Akimasa Saito, Masashi Imai
2024.9
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Developing and evaluating a quantum annealing simulator using QuTiP
Akimasa Saito, Masashi Imai
2024.8
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極低温環境におけるFPGA評価ボードの性能評価
高嶋智規,斉藤旭晟,今井雅
電子情報通信学会技術研究報告 VLD2024-131 160 - 165 2025.3
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量子アニーリングシミュレータと回路シミュレータの統合と有用性評価
斉藤旭晟,今井雅
電子情報通信学会技術研究報告 VLD2024-132 166 - 171 2025.3
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津軽弁アーカイブシステムおよび津軽弁辞書・コーパスの構
池田光里, 今井雅
情報処理学会東北支部研究報告 2024-7 ( 3-6 ) 2025.2
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設計制約を課した論理合成結果選択の妥当性に関する一考察
今井雅
電子情報通信学会技術研究報告 VLD2024-66 220 - 225 2024.11
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津軽弁翻訳システムの実用化に向けた一考察
斎藤遥大, 今井雅
第206回SLDM研究発表会 2024.11
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津軽弁アーカイブシステムに向けた津軽弁辞書・コーパスの構築
池田光里, 今井雅
第206回SLDM研究発表会 2024.11
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QuTiPを用いた量子アニーリングシミュレータの構築と評価
斉藤旭晟, 今井雅
DAシンポジウム2024 2024.8
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透明ディスプレイを用いた津軽弁翻訳システムの開発
斎藤遥大, 村上晃啓, 今井雅
DAシンポジウム2024 2024.8
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Energy Reduction of Health Monitoring Processor by Optimizing Supply and Back-Gate Voltages with Simulated Annealing
Seria Kasai, Yamato Ishida, Fumiya Sano, Tomoya Akasaka, Ma\ sami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Ima\ i, Atsushi Kurokawa, Toshiki Kanamoto
Proc. SASIMI2024 227 - 232 2024.3
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Development of Tsugaru Dialect Dictionary Management System
Ryota Sato, Masashi Imai
Proc. SASIMI2024 254 - 259 2024.3
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Evaluation of FPGA Performance in a Cryogenic Environment
Akimasa Saito, Masashi Imai
Proc. SASIMI2024 244 - 249 2024.3
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Development of Snowfall Prediction System using X-band Weather Radar and Artificial Intelligence
Atsushi Onodera, Masashi Imai
Proc. SASIMI2024 84 - 85 2024.3
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Development of an Automatic Chronological Record Creation System Using Voice AI to Facilitate Information Aggregation and Sharing in the Event of a Disaster.
Tsujiguchi T, Imai M, Kimura S, Koiwa T, Naraoka M, Hanada H, Yamanouchi K, Kashiwakura I, Ito K
Disaster medicine and public health preparedness 17 e560 2023.12
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A Study on the Implementation of Muller’s C-element in Synchronous Circuit Design Environment
Masashi Imai
IEICE Technical Report, VLD2023-79 255 - 260 2023.11
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非同期式回路を用いた電源喪失対応 VLSI システムの実現
今井雅
電子情報通信学会技術研究報告 VLD2022-86 79 - 84 2023.3
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Transformerを用いた津軽弁と共通語の双方向翻訳システムの構築
新井田大輝, 今井雅
情報処理学会東北支部研究報告 Vol.2022-7 ( No.4-4 ) 2023.2
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外れ値検知アルゴリズムによるハードウェアトロイ内包計算機に生じる誤りの検知
葛西巧朗, 今井雅
情報処理学会東北支部研究報告 Vol.2022-7 ( No.4-5 ) 2023.2
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低電圧環境に適した回路設計方式の比較
坂本昴, 今井雅
情報処理学会東北支部研究報告 Vol.2022-7 ( No.4-6 ) 2023.2
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ハードウェアトロイの挿入された計算機が齎す誤りの検知と対策,
葛西巧朗, 今井雅
電子情報通信学会技術研究報告 VLD2022-55 206 - 211 2022.11
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FPGA-SoMを用いたASIC試作チップ評価システムの構築
今井雅, 吉瀬謙二, 米田友洋
電子情報通信学会技術研究報告 VLD2022-19 1 - 6 2022.11
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Development of Text Translation System from Tsugaru Dialect into Common Japanese
Taiki Niida, Masashi Imai
163 - 167 2022.10
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Development of Diagnosis-based Hardware Trojan Tolerate System
Takuro Kasai, Masashi Imai
Proc. SASIMI2022 196 - 197 2022.10
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津軽弁から共通語への変換システムの構築
新井田大輝, 今井雅
Proc. DAシンポジウム2022 195 - 200 2022.9
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低電圧環境における同期式回路と非同期式回路の比較
坂本昴, 今井雅
Proc. DAシンポジウム2022 126 - 131 2022.9
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パターン密度均一化に貢献するオンチップデカップリング容量セルの提案
岡巧, 葛西瀬梨亜, 石田大和, 佐野文也, 今井雅, 金本俊幾
Proc. DAシンポジウム2022 207 - 211 2022.9
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Translate your Tsugaru-ben into common language: Hirodai×AI×Tsugaru-ben project
Imai Masashi
The Journal of Radiological Nursing Society of Japan 10 ( 1 ) 9 - 12 2022.6
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低消費エネルギープロセッサのSoC物理設計
葛西瀬梨亜, 畠山寛, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2021-6 ( 5-3 ) 2022.2
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An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring
Toshiki Kanamoto, Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara
Proc. of GCCE, 1 - 2 2021.10
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Novel Circuit Structure of Basic Standard Cells against Glitches
Masashi Imai
Proc. ASYNC2021 Fresh idea track paper 2021.9
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Prediction of Winter Precipitation from X-band Weather Radar Observations Using Deep Learning
Mio Maeda, Akiyo Yatagai, Masashi Imai
Proc. AOGS2021 2021.8
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Thermal design technology for non-low power hearables
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa
Proc. SASIMI2021 2021.3
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Energy efficient RISC-V processor for portable sensor applications
Kan Hatakeyama, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto
Proc. SASIMI2021 2021.3
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Thermal Network Model and Analysis of Hearable Devices
Kodai Matsuhashi, Masashi Imai, Toshiki Kanamoto, Atsushi Kurokawa
IPSJ Tohoku Branch SIG Technical Report 2021.2
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Utilization of Tsugaru-ben with Artificial Intelligence and Inheritance Activities of Tsugaru Culture
Masashi Imai, Yuko Sugiyama, Masatoshi Matsuzaki, Ruriko Kidachi, Chieko Itaki, Takenori Niioka, Takakiyo Tsujiguchi, Ikuo Kashiwakura
IPSJ Tohoku Branch SIG Technical Report 2021.2
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A Prediction of Snowfall using Hirodai Shirakami Radar and Deep Learning
Taiki Niida, Akiyo Yatagai, Masashi Imai
IPSJ Tohoku Branch SIG Technical Report 2021.2
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Device Structure Estimation of Trench-IGBT Based on the Data Sheet
Taisei Arima, Tsuneo Munakata, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2021.2
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Thermal Optimization for the Trimmed Shapes of the NiCr Thin Film Resistors to Improve the Pulse Durability
Ryo Arima, Shota Kajiya, Keita Izawa, Ryosuke Watanabe, Tomohiro Aoba, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2021.2
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Estimating Fish Weight with TOF-Camera
Daiki Oikawa, Tetsuya Nomura, Sumio Tanba, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2021.2
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On-chip Impedance Extraction for LSI, Package and Board Cooperative Design
Takumi Oka, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2021.2
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ひろだい白神レーダー及び深層学習を利用した降雪量推定
新井田大輝, 谷田貝亜紀代, 今井雅
情報処理学会東北支部研究報告 2020-6 ( 3-2 ) 2021.2
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耐パルス性NiCr薄膜抵抗器のトリミング形状に対する熱的最適化
有馬諒, 梶谷翔太, 伊澤敬太, 渡邊良祐, 青葉智寛, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-2 ) 2021.2
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人工知能による津軽弁の活用と津軽弁文化保存の取り組み
今井雅, 杉山祐子, 松﨑正敏, 木立るり子, 井瀧千恵子, 新岡丈典, 辻口貴清, 柏倉幾郎
情報処理学会東北支部研究報告 2020-6 ( 3-1 ) 2021.2
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データシートを用いたトレンチ型IGBTの素子構造推定
有馬大生, 宗形恒夫, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-1 ) 2021.2
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機械学習を用いたひろだい白神レーダによる冬季降雪量推定
谷田貝亜紀代, 今井雅, 前田未央
日本気象学会令和2年度東北地方調査研究会講演集 2020.12
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機械学習を用いたひろだい白神レーダによる冬季降雪量推定
谷田貝亜紀代, 今井雅, 前田未央
日本気象学会令和2年度東北地方調査研究会 2020.12
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Asynchronous Building Blocks and Their Application for Ultra Low Energy Devices
Imai Masashi
IEICE Proceeding Series 74 89 - 92 2020.11
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Asynchronous Building Blocks and Their Application for Ultra Low Energy Devices
Masashi Imai
Proc. NOLTA2020 2020.11
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A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis
Kanamoto Toshiki, Kasai Koki, Hatakeyama Kan, Kurokawa Atsushi, Nagase Tomoyuki, Imai Masashi
IEICE Electronics Express 17 ( 14 ) 20200198 - 20200198 2020.7
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Coarse Grained Versus Fine Grained Architectures for Asynchronous Reconfigurable Devices
Tomohiro Yoneda, Masashi Imai
Proc. ASYNC2020 2020.5
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Coarse Grained Versus Fine Grained Architectures for Asynchronous Reconfigurable Devices
Tomohiro Yoneda, Masashi Imai
Proc.ASYNC2020 102 - 110 2020.5
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Studies on Image Analysis and Reducing Power Consumption Towards Maintenance-Free Sensor Nodes
Takumi Hatase, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2020.2
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A Study on Low Power Sensor Node Communication using LoRa
Kan Hatakeyama, Sumio Tanba, Atsuhi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2020.2
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A Study on Equivalent Circuit Modeling of IGBT Towards Coupled Electro Thermal Stress Analysis for Power Module
Sota Ito, Tsuneo Munakata, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report, 2020.2
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Simulation-based On-chip Capacitance Extraction Method
Koki Kasai, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2020.2
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LPWA通信規格LoRaを用いたセンサノードの低消費電力通信の評価
畠山寛, 丹波澄雄, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-2 ) 2020.2
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メンテナンスフリーセンサノード実現に向けた画像分析と消費電力低減の検討
畑瀬拓実, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-3 ) 2020.2
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パワーモジュールの熱応力連成解析に向けたIGBT等価回路モデルに関する検討
伊藤颯汰, 宗形恒夫, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-1 ) 2020.2
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シミュレーションベースオンチップ電源容量抽出手法
葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 1-1 ) 2020.2
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Quantitative Performance Comparison of Asynchronous and Synchronous Comparators
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2019 296 - 297 2019.10
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Efficiency Investigation of Capacitors Mounted on Re-distribution Layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
Proc. SASIMI2019 176 - 179 2019.10
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Thermal Modeling and Simulation of a Smart Wrist-worn Wearable Device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. SASIMI2019 138 - 143 2019.10
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Efficiency Investigation of Capacitors Mounted on Re-distribution Layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
Proc. SASIMI2019 176 - 179 2019.10
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Thermal Modeling and Simulation of a Smart Wrist-worn Wearable Device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. SASIMI2019 138 - 143 2019.10
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Quantitative Performance Comparison of Asynchronous and Synchronous Comparators
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2019 296 - 297 2019.10
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A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
Proc. MWSCAS2019 1085 - 1088 2019.8
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A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
Proc. MWSCAS2019 1085 - 1088 2019.8
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Hardware Trojan Insertion and Detection in Asynchronous Circuits
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto
Proc.ASYNC2019 134 - 143 2019.5
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ASYNC2019
Masashi Imai
Proc. ASYNC2019 2019.5
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湘南会議No.133
Masashi Imai
湘南会議No.133報告 2019.5
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Neural network-based 3D IC interconnect capacitance extraction
Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa
Proc. ICCET2019 168 - 172 2019.4
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Neural network-based 3D IC interconnect capacitance extraction
Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
PROCEEDINGS OF 2019 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION ENGINEERING AND TECHNOLOGY (ICCET 2019) 168 - 172 2019.4
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リストウェアラブルデバイスのベルト放熱効果
岡本慎太郎, 松橋功大, 今井雅, 金本俊幾, 黒川敦
電気学会 全国大会 講演論文集 32 - 32 2019.3
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Implementation of Multiple Modular Redundancy System for Disabling Hardware Trojan
Junya Wajima, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IPSJ Tohoku Branch SIG Technical Report 2018-9 ( No. B3-2 ) 2019.2
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束データ方式非同期式回路におけるハードウェアトロイ検出手法の評価
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B3-3 ) 2019.2
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APHRODITEデータのDB化による品質管理およびweb上でのデータ公開について
谷田貝亜紀代, 今井雅, 前田未央, 石田祐宣
情報処理学会東北支部研究報告 2018-9 ( A2-3 ) 2019.2
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遅延ばらつきを考慮した遅延線設計による束データ方式非同期式回路の高性能化
赤坂親一郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B3-1 ) 2019.2
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ハードウェアトロイ無効化のための多重化システムの実装
和島純也, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B3-2 ) 2019.2
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Evaluation of Hardware Trojan Detection Method in Bundled-Data Asynchronous Circuits
Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IPSJ Tohoku Branch SIG Technical Report 2018-9 ( No. B3-3 ) 2019.2
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AC解析を用いたオンチップ電源分配網の容量抽出手法
葛西孝己, 黒川敦, 今井雅, 金本俊幾
情報処理学会 東北支部研究会 2019.2
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Performance Improvement of Bundled-Data Asynchronous Circuit by Delay-line Design Considering Delay Variation
Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IPSJ Tohoku Branch SIG Technical Report 2018-9 ( B3-1 ) 2019.2
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Quality Control by Making a Database (DB) of Station Precipitation Data for APHRODITE and Product Release via the Web-Site
Akiyo Yatagai, Masashi Imai, Mio Maeda, Sachinobu Ishida
IPSJ Tohoku Branch SIG Technical Report 2018-9 ( No. A2-3 ) 2019.2
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束データ方式非同期式回路におけるハードウェアトロイ攻撃と対策
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会ハードウェアセキュリティフォーラム2018 2018.12
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MTJ-based Asynchronous Circuits for Re-initialization Free Computing Against Power Failures
N. Onizawa, M. Imai, T. Yoneda, T. Hanyu,
Microelectronics Journal 82 46 - 61 2018.10
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SATソルバによるADC解法研究のすすめ
鈴木隆士, 海野和貴, 眞鍋雄太, 秋元恭太, 赤坂親一郎, 稲葉光太郎, 和島純也, 今井雅
DAシンポジウム2018 2018.8
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2phaseハンドシェイクプロトコルに基づく束データ方式非同期式回路のレプリカ遅延線設計
赤坂親一郎, 金本俊幾, 黒川敦, 今井雅
DAシンポジウム2018 93 - 98 2018.8
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An Efficient Implementation Method and Development of Demonstration Environment for Byzantine Fault Tolerant Systems
Masashi Imai, Takeru Nanao, Yudai Ishikawa, Koutaro Inaba
IEICE Technical Report, DC2018-15 (SWOPP2018) 13 - 18 2018.7
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Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols
Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
Proc. ASYNC2018 1 - 8 2018.5
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Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Yuuta Satomi, Koutaro Hachiya, Masashi Imai,ToshikiKanamoto,KaoruFurumi,AtsushiKurokawa
Proc. SASIMI2018 2018.3
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Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. SASIMI2018 394 - 397 2018.3
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Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Masashi Imai, Naoya Onizawa, Takahiro Hanyu, Tomohiro Yoneda
Proc. SASIMI2018 283 - 288 2018.3
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ビザンチンフォールトトレラントシステムの構築と実用性評価
七尾健, 石川雄大, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018.2
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容量素子最適化のための LSI・パッケージ・ボード電源網解析モデルの構築
葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2018.2
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PowerMOS デバイス熱設計のためのボンディングワイヤモデルの構築
太田拓磨, 宗形恒夫, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2018.2
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CMOS回路における消費エネルギー低減のための電源電圧と閾値電圧の調節手法
成田全, 葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2018.2
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FPGA の信号伝搬遅延の温度依存性に関する研究
江良祥耶, 葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2018.2
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ランダム遅延素子を用いた耐タンパ非同期式回路の設計
豊嶋太樹, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018.2
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MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
Proceedings - International Symposium on Asynchronous Circuits and Systems 2017- 118 - 125 2017.11
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容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陈俊, 神藤始
DAシンポジウム2017論文集 2017.8
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Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Seira Kamiie, Toshiki Kanamoto, Masashi Imai, Shintaro Okamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 1806 2017.8
-
容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築
葛西孝己, 今井雅, 黒川敦, 金本俊幾, 陈俊, 橋本昌宜, 神藤始
平成29年度電気関係学会東北支部連合大会 2017.8
-
PowerMOSデバイス熱設計のためのボンディングワイヤモデルの構築
太田拓磨, 葛西孝己, 今井雅, 黒川敦, 金本俊幾, 宗形恒夫
平成29年度電気関係学会東北支部連合大会 2017.8
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Estimating Walking State When Holding Object in Hand by Using Neural Network
Ryo Sasaki, Toshiki Kanamoto, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
ランダム遅延素子を用いた非同期式回路の耐タンパ性向上に関する一考察
豊嶋太樹, 金本俊幾, 黒川敦, 今井雅
平成29年度電気関係学会東北支部連合大会 2017.8
-
Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Shintaro Okamoto, Kaoru Furumi, Masashi Imai, Toshiki Kanamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Yuta Satomi, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
Reducing Temperature by Relocating 3D IC Structures
Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
Hardware Trojan Comparison between Synchronous and Asynchronous Circuits
Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
Thermal-Aware Tile-Based Block Placement for 3D ICs
Ryosuke Hatsuta, Masashi Imai, Toshiki Kanamoto, Shintaro Okamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers 2017.8
-
A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1B10 2017.8
-
LSI-Package-Board Power Delivery Network Modeling for Capacitor Placement Optimization at 15nm Node
Toshiki Kanamoto, Koki Kasai, Masashi Imai, Atsushi Kurokawa, Masanori Hashimoto, Jun Chen, Hajime Kando
Proc. DAS2017 111 - 114 2017.8
-
容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築
葛西孝己, 今井雅, 黒川敦, 金本俊幾, 陈俊, 橋本昌宜, 神藤始
平成29年度電気関係学会東北支部連合大会 2E09 2017.8
-
ランダム遅延素子を用いた非同期式回路の耐タンパ性向上に関する一考察
豊嶋太樹, 金本俊幾, 黒川敦, 今井雅
平成29年度電気関係学会東北支部連合大会 1G04 2017.8
-
Reducing Temperature by Relocating 3D IC Structures
Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1B15 2017.8
-
PowerMOSデバイス熱設計のためのボンディングワイヤモデルの構築
太田拓磨, 葛西孝己, 今井雅, 黒川敦, 金本俊幾, 宗形恒夫
平成29年度電気関係学会東北支部連合大会 2E03 2017.8
-
Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Yuta Satomi, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1B16 2017.8
-
Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Seira Kamiie, Toshiki Kanamoto, Masashi Imai, Shintaro Okamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1B06 2017.8
-
Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Shintaro Okamoto, Kaoru Furumi, Masashi Imai, Toshiki Kanamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1B17 2017.8
-
Estimating Walking State When Holding Object in Hand by Using Neural Network
Ryo Sasaki, Toshiki Kanamoto, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2B19 2017.8
-
耐ビザンチンフォールトシステムの実装方式に関する一考察
七尾健, 石川雄大, 今井雅
電子情報通信学会技術研究報告DC2017-17 7 - 12 2017.7
-
Task Scheduling based Redundant Task Allocation Method for the Multi-core Systems with the DTTR Scheme
100 ( 7 ) 1363 - 1773 2017.7
-
A Study on Implementation Method of Byzantine Fault Tolerant Systems
Takeru Nanao, Yudai Ishikawa, Masashi Imai
IEICE Technical Report, DC2017-17 (SWOPP2017) 7 - 12 2017.7
-
非同期式オンチップネットワークルータに対するハードウェアトロイ挿入
稲葉光太郎, 今井雅
電子情報通信学会ハードウェアセキュリティ研究会 2017.6
-
A Study on Hardware Trojan Insertion into Asynchronous NoC Router
Koutaro Inaba, Tomohiro Yoneda, Masashi Imai
2017.5
-
MTJ-Based Asynchronous Circuits for Re-initialization Free Computing against Power Failures
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
118 - 125 2017.5
-
A Study on Hardware Trojan Insertion into Asynchronous NoC Router
Koutaro Inaba, Tomohiro Yoneda, Masashi Imai
Proc. Async2017 Fresh ideas track paper 2017.5
-
Cooling Architectures using Thermal Sidewalls, Interchip Plates, and Bottom Plate for 3D ICs
Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
Proc. ISQED2017 2017.3
-
非同期式NoCルータへのハードウェアトロイ挿入に関する研究
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会総合大会 A-7-1 2017.3
-
マルチコアシステムのマルコフモデルによる信頼性評価
和島純也, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会総合大会 D-10-3 2017.3
-
A Study on Hardware Trojan Insertion in Asynchronous NoC Router
Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IEICE Technical Report A-7-1 82 - 82 2017.3
-
極低電圧回路における消費エネルギー極小化に関する一考察
瀧健太郎, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2016-6 ( B1-1 ) 2017.2
-
低電圧環境における高性能非同期式回路の実現
田近龍平, 金本俊幾, 今井雅
情報処理学会東北支部研究報告 2016-6 ( B1-4 ) 2017.2
-
ハンドシェイク回路多重化による低ノイズ非同期式回路の実現,
石川達也, 金本俊幾, 今井雅
情報処理学会東北支部研究報告 2016-6 ( B1-3 ) 2017.2
-
多段リングオシレータによるFPGA性能ばらつきの実験的評価
増川孔明, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2016-6 ( B1-2 ) 2017.2
-
Hardware Trojan Comparison between Synchronous and Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 19 - 19 2017
-
A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 21 - 21 2017
-
容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築
葛西 孝己, 今井 雅, 黒川 敦, 金本 俊幾, 陳 俊, 橋本 昌宜, 神藤 始
電気関係学会東北支部連合大会講演論文集 2017 ( 0 ) 201 - 201 2017
-
ランダム遅延素子を用いた非同期式回路の耐タンパ性向上に関する一考察
豊嶋 太樹, 金本 俊幾, 黒川 敦, 今井 雅
電気関係学会東北支部連合大会講演論文集 2017 ( 0 ) 94 - 94 2017
-
Thermal-Aware Tile-Based Block Placement for 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 18 - 18 2017
-
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme
SAITO Hiroshi, IMAI Masashi, YONEDA Tomohiro
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A ( 7 ) 1363 - 1373 2017
-
Reducing Temperature by Relocating 3D IC Structures
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 26 - 26 2017
-
PowerMOSデバイス熱設計のためのボンディングワイヤモデルの構築
太田 拓磨, 葛西 孝己, 今井 雅, 黒川 敦, 金本 俊幾, 宗形 恒夫
電気関係学会東北支部連合大会講演論文集 2017 ( 0 ) 196 - 196 2017
-
Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 27 - 27 2017
-
Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 17 - 17 2017
-
Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 28 - 28 2017
-
Estimating Walking State When Holding Object in Hand by Using Neural Network
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 165 - 165 2017
-
非同期式回路に対するハードウェアトロイ挿入に関する一考察
稲葉光太郎, 今井雅
ハードウェアセキュリティフォーラム2016 ポスター発表 2016.12
-
非同期式回路に対するハードウェアトロイ挿入に関する一考察
稲葉光太郎, 今井雅
ハードウェアセキュリティフォーラム2016 ポスター 2016.12
-
Hardware Trojan Insertion Difficulties into Synchronous and Asynchronous Circuits
Masashi Imai, Tomohiro Yoneda
Proc. SASIMI2016 213 - 218 2016.10
-
Random Delay Elements for Tamper Resistant Asynchronous Circuits based on 2-phase Handshaking Protocol
Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2016 113 - 118 2016.10
-
The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
Proc. NOCS2016 64 - 69 2016.9
-
ラッチベース非同期式回路のスキャンテスト
寺山恭平, 今井雅
電子情報通信学会論文誌A 99-A ( 8 ) 298 - 308 2016.8
-
A Study on Byzantine Fault Tolerant Systems using SCore Cluster System Software
Takeru Nanao, Atsushi Kurokawa, Masashi Imai
2A07 2016.8
-
Recognition of Wrist Position While Walking by Using Wearable Triaxial Accelerometers
Kaoru Furumi, Shintaro Mizoguchi, Nanako Niioka, Masashi Imai, Atsushi Kurokawa
Proc. ITC-CSCC2016 97 - 100 2016.7
-
ランダム遅延素子を用いた耐タンパ非同期式パイプライン回路
豊嶋太樹, 黒川敦, 今井雅
電子情報通信学会 技術研究報告 VLD2016-40 185 - 190 2016.6
-
マルチソースバッファを用いた積層チップのクロック分配方法
新岡七奈子, 古見薫, 今井雅, 黒川敦
電子情報通信学会 技術研究報告 VLD2016-37 167 - 172 2016.6
-
三次元集積回路の熱解析
古見薫, 今井雅, 新岡七奈子, 黒川敦
電子情報通信学会 技術研究報告 VLD2016-38 173 - 178 2016.6
-
多数決イネーブルラッチを用いた非同期式回路の耐故障性に関する一検討
今井雅, 米田友洋
電子情報通信学会 技術研究報告 VLD2016-39 179 - 184 2016.6
-
Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements
Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai
IEICE Technical Report VLD2016-40 185 - 190 2016.6
-
"A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches
Masashi Imai, Tomohiro Yoneda
IEICE Technical Report VLD2016-39 179 - 184 2016.6
-
Can Asynchronous Circuits Tolerate Hardware Trojan Threat?
Masashi Imai, Tomohiro Yoneda
Proc. ASYNC2016 2016.5
-
A Task Allocation Method for the DTTR Scheme based on Task Scheduling of Fault Patterns
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
Proc. ISCAS2016 2016.5
-
Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems
Tomohiro Yoneda, Naoya Onizawa, Masashi Imai, Takahiro Hanyu
Proc. ASYNC2016 2016.5
-
ウェアラブルセンサを用いた歩行時の腕の状態認識
溝口真太郎, 深瀬政秋, 今井雅, 古見薫, 新岡七奈子, 黒川敦
情報処理学会第78回全国大会, 1V-01 2016.3
-
ラッチベース非同期式回路のテストに関する研究
寺山恭平, 今井雅
情報処理学会東北支部研究報告 Vol.2015-8 No.B1-2 2016.2
-
DTTR方式によるマルチコアシステム向けのタスクの最大並列度を基にしたタスク割り当て手法
齋藤寛, 今井雅, 米田友洋
電子情報通信学会技術研究報告 VLD2015-113 13 - 18 2016.2
-
ディペンダブル・ネットワーク・オンチッププラットフォームの開発に関する研究
佐藤謙介, 今井雅
情報処理学会東北支部研究報告 Vol.2015-8 No.B1-1 2016.2
-
Research on Test Method of Latch-based Asynchronous Circuits
Kyohei Tereyama, Masashi Imai
IPSJ Tohoku Branch SIG Technical Report Vol. 2015-8 ( No. B1-2 ) 2016.2
-
A Study on Byzantine Fault Tolerant Systems using SCore Cluster System Software
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2016 ( 0 ) 26 - 26 2016
-
ラッチベース非同期式回路のスキャンテスト
今井 雅
電子情報通信学会論文誌 J99-A 2016
-
非同期式回路を用いたピーク電流抑制型バンドパスフィルタの実装と評価
石川達也, 黒川敦, 今井雅
電子情報通信学会 技術研究報告 VLD2015-68,DC2015-64 195 - 200 2015.12
-
QDIモデルに基づく非同期式VLSIの低電圧特性の評価
田近龍平, 黒川敦, 今井雅
電子情報通信学会 技術研究報告 VLD2015-67,DC2015-63 189 - 194 2015.12
-
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai
IEICE Technical Report VLD2015-68, DC2015-64 195 - 200 2015.12
-
DTTR方式によるマルチコアシステムの信頼性向上のためのタスク割り当て手法の検討
齋藤寛, 米田友洋, 今井雅
情報処理学会研究報告 Vol.2015-SLDM-172 No.12 63 - 68 2015.10
-
DTTR方式による高信頼マルチコアシステムの性能評価に関する一考察
佐藤謙介, 齋藤寛, 米田友洋, 今井雅
情報処理学会研究報告 Vol.2015-SLDM-172 No.11 57 - 62 2015.10
-
A New Encoding Mechanism for Low Power Inter-Chip Serial Communication in Asynchronous Circuits
Tomohiro Yoneda, Masashi Imai
Proc. ICCD2015 Poster Session 424 - 427 2015.10
-
Dependable Real-Time Task Execution Scheme for a Many-Core Platform
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
Proc. DFTS2015 198 - 205 2015.10
-
Clock Skew Reduction for Stacked Chips Using Multiple Source Buffers
Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa
Proc. ISCIT2015 2015.10
-
A New Encoding Mechanism for Low Power Inter-Chip Serial Communication in Asynchronous Circuits
Tomohiro Yoneda, Masashi Imai
Proc. ICCD2015 Poster session 424 - 427 2015.10
-
Clock Skew Reduction for Stacked Chips Using Multiple Source Buffers
Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa
Proc. ISCIT2015 2015.10
-
A Study on Performance Evaluation of Highly Reliable Multiple-Core Systems
Kensuke Sato, Hirosahi Saito, Tomohiro Yoneda, Masashi Imai
IPSJ SIG Technical Report Vol. 2015-SLDM-172 ( No. 11 ) 57 - 62 2015.10
-
DTTR方式によるマルチコアシステムの信頼性向上のためのタスク割り当て手法の検討
齋藤寛, 米田友洋, 今井雅
情報処理学会研究報告 Vol. 2015-SLDM-172 ( No. 12 ) 63 - 68 2015.10
-
Dependable Real-Time Task Execution Scheme for a Many-Core Platform
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
Proc. DFTS2015 198 - 205 2015.10
-
Comparing Permanent and Transient Fault Tolerance of Multiple-core based Dependable ECUs
Masashi Imai, Tomohiro Yoneda
Proc. CARS2015 2015.9
-
Performance Comparison between Asynchronous Self-timed Circuits and Synchronous Circuits under Ultra Low Voltage Environment
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai
平成27年度電気関係学会東北支部連合大会, IEEE Student Session, 1A08 2015.8
-
Peak Current Reduction Method of Digital Bandpass Filter using Asynchronous MOUSETRAP Pipeline Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai
平成27年度電気関係学会東北支部連合大会 IEEE Student Session, 1A09 2015.8
-
Thermal Analysis with Varying Physical Parameters in 3D ICs
Kaoru Furumi, Masaaki Fukase, Masashi Imai, Yuuki Miura, Nanako Niioka, Atsushi Kurokawa
電気学会 電子・情報・システム部門大会 2015.8
-
三次元集積回路の伝搬遅延とクロストークノイズのモデリング
新岡七奈子, 深瀬政秋, 今井雅, 古見薫, 三浦祐輝, 黒川敦
第28回 回路とシステムワークショップ 2015.8
-
Duplication with Temporary Triple Modular Redundancy and Reconfigurationのためのタスク割り当て手法
齋藤寛, 米田友洋, 今井雅
Proc. DAS2015 2015.8
-
三次元集積回路の伝搬遅延とクロストークノイズのモデリング
新岡七奈子, 深瀬政秋, 今井雅, 古見薫, 三浦祐輝, 黒川敦
第28回 回路とシステムワークショップ 2015.8
-
Thermal Analysis with Varying Physical Parameters in 3D ICs
Kaoru Furumi, Masaaki Fukase, Masashi Imai, Yuuki Miura, Nanako Niioka, Atsushi Kurokawa
電気学会 電子・情報・システム部門大会 2015.8
-
Performance Comparison between Asynchronous Self-timed Circuits and Synchronous Circuits under Ultra Low Voltage Environment
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A08 2015.8
-
Peak Current Reduction Method of Digital Bandpass Filter using Asynchronous MOUSETRAP Pipeline Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A09 2015.8
-
DTTR方式による高信頼メニコアシステムの性能評価
今井雅, 米田友洋
FTC研究会 2015.7
-
A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai
IEICE Technical Report DC2015-19 19 - 24 2015.6
-
Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai, Tomohiro Yoneda
IEICE Technical Report DC2015-20 25 - 30 2015.6
-
Scan test of latch-based asynchronous pipeline circuits under 2-phase handshaking protocol
Kyohei Terayama, Atsushi Kurokawa, Masashi Imai
Proc. of SASIMI2015 128 - 133 2015.3
-
ウィンドウベースL逆行列によるTSV間容量抽出
小林徹哉, 今井雅, 深瀬政秋, 新岡七奈子, 黒川敦,
電子情報通信学会 総合大会 講演論文集 2015.3
-
高効率遅延セルの実測による性能評価
星誠, 深瀬政秋, 今井雅, 黒川敦
電子情報通信学会 総合大会 講演論文集 2015.3
-
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs
Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-aki Fukase, Masashi Imai, and Atsushi Kurokawa
Proc. of ISQED2015 2015.3
-
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs
Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-aki Fukase, Masashi Imai, Atsushi Kurokawa
Proc. ISQED15 2015.3
-
高効率遅延セルの実測による性能評価
星誠, 深瀬政秋, 今井雅, 黒川敦
電子情報通信学会総合大会 2015.3
-
ウィンドウベースL逆行列によるTSV間容量抽出
小林徹哉, 今井雅, 深瀬政秋, 新岡七奈子, 黒川敦
電子情報通信学会総合大会 2015.3
-
Scan test of latch-based asynchronous pipeline circuits under 2-phase handshaking protocol
Kyohei Terayama, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2015 128 - 133 2015.3
-
Novel Implementation Method of Multiple-Way Asynchronous Arbiters
IMAI Masashi, YONEDA Tomohiro
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A ( 7 ) 1519 - 1528 2015
-
Signal Propagation Delay Model in Vertically Stacked Chips
NIIOKA Nanako, WATANABE Masayuki, FUKASE Masa-aki, IMAI Masashi, KUROKAWA Atsushi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A ( 12 ) 2614 - 2624 2015
-
Performance Comparison between Asynchronous Self-timed Circuits and Synchronous Circuits under Ultra Low Voltage Environment
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2015 ( 0 ) 8 - 8 2015
-
Peak Current Reduction Method of Digital Bandpass Filter using Asynchronous MOUSETRAP Pipeline Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2015 ( 0 ) 9 - 9 2015
-
Energy-and-Performance Efficient Differential Domino Logic Cell Libraries for QDI-model-based Asynchronous Circuits
Masashi Imai, Tomohiro Yoneda
Proc. of APCCAS2014 687 - 690 2014.11
-
Effect of Substrate Contacts on Reducing Crosstalk Noise between TSVs
Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-aki Fukase, Masashi Imai, Atsushi Kurokawa
Proc. of APCCAS2014 763 - 766 2014.11
-
An NoC-based Evaluation Platform for Safety-Critical Automotive Applications
omohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
Proc. of APCCAS2014 679 - 682 2014.11
-
Impact of On-Chip Interconnects on Vertical Signal Propagation in 3D ICs
Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-aki Fukase, and Atsushi Kurokawa
Proc. of APCCAS2014 2014.11
-
A Study of Multi-way Arbiter Implementation Methods for High-Speed Communication Asynchronous Circuits
Masashi Imai, Atsushi Kurokawa
IEEJ Society C 771 - 776 2014.9
-
Scan Test of Asynchronous Circuits based on 2Phase Handshaking Protocol
Kyohei Terayama, Masashi Imai, Atsushi Kurokawa
IEEJ Society C 765 - 770 2014.9
-
Synthesis Library for Asynchronous Fine-grain Pipeline Circuits using DDL Elements
Masashi Imai
73 - 78 2014.8
-
Modeling and analysis of vertical interconnects in 3D ICs
Nanako Niioka, Masashi Imai, Masa-aki Fukase, Rosely Karel, Tetsuya Koba\ yashi, and Atsushi Kurokawa
Proc. Tohoku-Section J\ oint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A03 2014.8
-
Substrate contact effect on TSV-to-TSV coupling
Rosely Karel, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Koba\ yashi, and Atsushi Kurokawa
Proc. Tohoku\ -Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A04 2014.8
-
Synthesis Library for Asynchronous Fine-grain Pipeline Circuits using DDL Elements
Masashi Imai
Proc DAS2014 73 - 78 2014.8
-
Substrate contact effect on TSV-to-TSV coupling
Rosely Karel, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Atsushi Kurokaw
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A04 2014.8
-
Modeling and analysis of vertical interconnects in 3D ICs
Nanako Niioka, Masashi Imai, Masa-aki Fukase, Rosely Karel, Tetsuya Kobayashi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A03 2014.8
-
Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking Asynchronous Circuits
Masashi Imai, Tomohiro Yoneda
Proc. ISCAS2014 2014.6
-
The Frontline of Dependable VLSI Systems 2014
Masashi Imai
2014.6
-
High-Throughput Partially Parallel Inter-chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Tadahiro Hanyu
IEICE Trans on Inf.&Syst. E97-D ( 6 ) 1546 - 1556 2014.6
-
The Frontline of Dependable VLSI Systems 2014
Masashi Imai
WIT2014 2014.6
-
Construction of Design Environment for Asynchronous Circuits using DDL Cell Library
Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo
Technical Report of IEICE 3 - 8 2014.4
-
Scan test of MOUSETRAP pipeline circuit
Kyohei Terayama, Masashi Imai
49 - 49 2014.3
-
Modeling and Analysis of Vertical Interconnects in 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2014 ( 0 ) 3 - 3 2014
-
Substrate Contact Effect on TSV-to-TSV Coupling
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2014 ( 0 ) 4 - 4 2014
-
Variability Evaluation and Characterization of Multi-clock Dual-Edge-Triggered FlipFlops
Masashi Imai, Tomohiro Yoneda
Proc. IEEE/ACM Workshop on Variability Modeling and Characterization 2013 2013.11
-
Proposal of Double-clock and Dual-Edge-Triggered Flip-Flops for Asynchronous Circuits
VLD2013 2013.10
-
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
Masashi Imai, Tomohiro Yoneda
IEICE Trans on Inf.&Syst. E96-D ( 9 ) 1914 - 1925 2013.9
-
Hetero-timing Circuit Design using Multi-Clock Dual-Edge-Triggered Flip-Flops
870 - 875 2013.9
-
High Performance Asynchronous Circuit Design using Multi-bit Storage Cells
864 - 869 2013.9
-
可変クロック方式の開発
小田桐舞央,今井雅,黒川敦,深瀬政秋
電気関係学会東北支部連合大会 1C04 2013.8
-
Development of a built-in clock circuit
2013.3
-
7.3 Asynchronous Networks-on-Chip(7. Responsiveness,<Special Survey>Dependable VLSI System)
YONEDA Tomohiro, IMAI Masashi
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 482 - 482 2013
-
10.5 Fault Detection and Reconfiguration Method for Multiple CPU Cores(10. Future and / or Un-Identified Problems,<Special Survey>Dependable VLSI System)
IMAI Masashi, YONEDA Tomohiro
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 514 - 514 2013
-
可変クロック方式の開発
小田桐 舞央, 今井 雅, 黒川 敦, 深瀬 政秋
電気関係学会東北支部連合大会講演論文集 2013 ( 0 ) 32 - 32 2013
-
Performance Modeling and Analysis of On-chip Networks for Real-time Applications
Masashi Imai, Tomohiro Yoneda
Proc. of PRDC2012 111 - 120 2012.11
-
Multi-Chip NoCs for Automotive Applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proc. PRDC2012 105 - 110 2012.11
-
Floorplan Method for SDI-model-based Asynchronous Circuits to Achieve High Robustness against Delay Variations
Masashi Imai, Tomohiro Yoneda
IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems 2012 2012.11
-
Dependable Routing in Multi-Chip NoC Platforms for Automotive Applications
Tomohiro Yoneda, Masashi Imai
Proc. DFT2012 217 - 224 2012.10
-
A Study of Placed-and-Routed Design Method for High-Performance Asynchronous Circuits Considering Delay Constraints
1137 - 1142 2012.9
-
Multi-chip NoCs for automotive applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 105 - 110 2012
-
Performance modeling and analysis of on-chip networks for real-time applications
Masashi Imai, Tomohiro Yoneda
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 111 - 120 2012
-
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
Masashi Imai, Tomohiro Yoneda
Proc. DFT2011 463 - 471 2011.10
-
Improrving Dependability and Performance of Fully Asynchronous On-chip Networks
Masashi Imai, Tomohiro Yoneda
Proc. Async2011 65 - 76 2011.4
-
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors
James Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. PRDC2010 62 - 69 2010.12
-
A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
VLD2010 ( 66 ) 67 - 72 2010.11
-
DSN2010 Report
DC2010 ( 23 ) 31 - 34 2010.10
-
Evaluation of Delay Variations and Soft-Error Hardness in Asynchronous Pipeline Circuits
Masashi Imai, Tomohiro Yoneda
Proc. IEEE/ACM Workshop on Variability Modeling and Characterization 2010.10
-
A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura
IEICE Technical Report VLD2010-66 67 - 72 2010.10
-
Hard-redundant Fault Tolerance Techniques for Resilient Protection Relay Systems
Tomoyuki Kawasaki, Katsuhiko Sekiguchi, Kazuto Fukushima, Takaya Shono, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. 16th International Conference on Electrical Engineering 2010.7
-
Pair and Swap: An Approach to Graceful Degradation for Dependable Chip Multiprocessors
Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. WDSN10 119 - 124 2010.6
-
An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
VLD2009 ( 51 ) 67 - 72 2009.12
-
An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya
IEICE Technical Report VLD2009-51,DC2009-38 67 - 72 2009.12
-
N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD09 125 - 130 2009.10
-
N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD2009 125 - 130 2009.10
-
Principles of Asynchronous Design Style
2009.7
-
Achieving Degradation Tolerance in a Hardware Accelerator with Parallel Functional Units
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Atsushi Matsumoto
Proc. of Third Workshop on Dependable and Secure Nanocomputing 28 - 33 2009.6
-
Fine-grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-Threshold-Voltage Transistors
Masashi Imai, Kouei Takada, Takashi Nanya
Proc. Async2009 209 - 216 2009.5
-
Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
VLD2008 ( 90 ) 183 - 188 2008.11
-
Performance Comparison between Self-timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors
Masashi Imai, Takashi Nanya
Proc. DSN08 2nd Workshop on Dependable and Secure Nanocomputing C23 - C28 2008.6
-
A Method of Priority Control for Low-Power in Chip Multiprocessors
317 - 324 2008.6
-
A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries
Masashi Imai, Takashi Nanya
Proc. ACSD08 21 - 26 2008.6
-
共有資源の優先度制御によるチップ・マルチプロセッサの小電力化手法
椎名公康, 近藤正章, 今井雅, 中村宏, 南谷崇
先進的計算基盤システムシンポジウム SACSIS 2008 317 - 324 2008.6
-
An approach to tolerating delay faults based on asynchronous circuits
2008.4
-
An Approach to Tolerating Delay Faults based on Asynchronous Circuits
Tomohiro Yoneda, Masashi Imai, Atsushi Matsumoto, Takahiro Hanyu, Yuichi Nakamura
IEICE Technical Report 2008.4
-
A Process-variation-aware low-power technique using current control
VLD2007 ( 76 ) 37 - 42 2007.11
-
A Method of Priority and Voltage/Frequency Control for Low-Power in Chip Multiprocessors
ARC-175 83 - 88 2007.11
-
A Plan of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs
ARC-173 79 - 84 2007.5
-
Design Method of High Performance and Low Power Functional Units Considering Delay Variations
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
IEICE Trans on Fundamentals E89-A ( 12 ) 3519 - 3528 2006.12
-
A Novel Checkpointing for Cluster System with Non-uniform Failure-Rate
J89-D ( 8 ) 1705 - 1716 2006.8
-
Overhead-Conscious Task Scheduling Scheme for Reducing Energy Consumption of Multi-Processor System-on-Chip
ARC-169 67 - 72 2006.8
-
Low Power Delay-Insensitive Asynchronous Circuits using 1-out-of-4 Encoding
ICD2006 ( 82 ) 19 - 24 2006.8
-
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations
Masashi Imai, Takashi Nanya
Proc. Async2006 68 - 77 2006.3
-
遅延変動特性を考慮したタイミング信号設計方式に関する検討
今井 雅,渡邊孝一,近藤正章,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2005 ( 59 ) 31 - 36 2005.11
-
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
VLD2005 ( 60 ) 37 - 42 2005.11
-
Task and Voltage Scheduling for Reducing Energy Consumption on GALS System-on-Chip
ARC-164 61 - 66 2005.8
-
Initial Discussion about Adaptive Checkpointing for HPC Cluster in View of Fluctuate of Failure-Rate
DC2005 ( 14 ) 7 - 12 2005.8
-
A Novel Design Method using Delay-Variation-Aware Cell Libraries for Asynchronous Bundled-data Transfer Circuits
Masashi Imai, Chikaaki Kogure, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Proc. ITC-CSCC2005 441 - 442 2005.7
-
Single Latched Scan Registers based on Multi-Clock for Low Heat Dissipation and for Low IR-Drop
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
Proc. ITC-CSCC2005 945 - 946 2005.7
-
A Design Method for a Standard Cell Library Considering Delay Variation
VLD2004 ( 63 ) 13 - 18 2004.12
-
Skewed Checkpointing for Tolerating Multi-Node Failures
Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
Proc. SRDS2004 116 - 125 2004.10
-
Asynchronous scan-latch controller for low area overhead DFT
M.Tsukisaka, M.Imai, T.Nanya
Proc. ICCD2004 66 - 71 2004.10
-
A Synthesis Method of Asynchronous Control Circuits from a Behaviroal Description
289 - 294 2004.7
-
Skewed Checkpointing for Tolerating Multi-Node Failures in Cluster System
DC2004 ( 19 ) 37 - 42 2004.7
-
Design Space Reduction Filter in Asynchronous Data-path Synthesis
295 - 300 2004.7
-
Evaluation of Delay Variation in Asynchronous Circuits based on the Scalable-Delay-Insensitive Model
Masashi Imai,Metehan Ozcan,Takashi Nanya
Proc. Async2004 62 - 71 2004.4
-
Synthesis of serial local clock controllers for asynchronous circuit design
N.Sretasereekul, H.Saito, E.Kim, M.Imai, M.Ozcan, H.Nakamura, T.Nanya
IEICE Trans on Fundamentals E86-A12 3028 - 3037 2003.12
-
Evaluation of Checkpointing Mechanism on SCore Cluster System
Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Atsushi Hori
IEICE Trans on Inf.&Syst., E86-D ( 12 ) 2553 - 2563 2003.12
-
同期式仕様記述を用いた非同期式VLSI設計支援CADシステムの構築と評価
今井 雅,Metehan Ozcan,小暮千賀明,齋藤 寛,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 84 ) 85 - 90 2003.11
-
セルコントローラに基づいた非同期式制御回路の合成
齋藤 寛,川鍋昌紀,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 83 ) 79 - 84 2003.11
-
非同期データパス合成における解探索空間の削減
川鍋昌紀,齋藤 寛,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 82 ) 73 - 78 2003.11
-
Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits
Metehan Ocan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Trans. of IPSJ 44 ( 5 ) 1244 - 1254 2003.5
-
A zero-time-overhead asynchronous four-phase controller
N.Sretasereekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nakamura, T.Nanya
Proc. ISCAS2003 205 - 208 2003.5
-
Control signal sharing using data-path delay information at control data flow graph description
H.Saito, E.Kim, N.Sretasereekul, M.Imai, H.Nakamura, T.Nanya
Proc. Async2003 184 - 193 2003.5
-
Control signal sharing of asynchroonous circuits using datapath delay information
H.Saito, E.Kim. M.Imai, N.Sretasereekul, H.Nakamura, T.Nanya
Proc. ISCAS2003 617 - 620 2003.5
-
Design and Evaluation of High Performance Microprocessor with Reconfigurable On-Chip Memory
Taku Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
Proc. APCCAS2002 211 - 216 2002.12
-
Analysis on Checkpointing Mechanism of SCore Cluster System
T.Hayashida, M.Kondo, M.Imai, H.Nakamura, T.Nanya, and A.Hori
Fastabstract of IEEE PRDC02 1 - 2 2002.12
-
Flexible Partitioning of CDFGs for Compact Asynchronous Controllers
Nattha Sretasereekul, Y. Okuyama, H. Saito, M. Imai, K. Kuroda, T. Nanya
Proc. International Technical Conference on Circuits/Systems, Computers and Communications 1724 - 1727 2002.7
-
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchrounous Data-Path Circuits
Metehan Ozcan, Masashi Imai, Takashi Nanya
Proc. Async2002 109 - 114 2002.4
-
Prospect of a stanniocalcin endocrine/paracrine system in mammals.
Ishibashi K, Imai M
American journal of physiology. Renal physiology 282 ( 3 ) F367 - 75 2002.3
-
遅延情報を利用した非同期式VLSI設計の一手法の提案
今井 雅,南谷 崇
電子情報通信学会技術研究報告 VLD2001 ( 120 ) 51 - 57 2001.11
-
Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, Takashi Nanya
Proc. Async2001 162 - 172 2001.3
-
A Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, Takashi Nanya
IEICE Trans. on Electronics E84-C ( 2 ) 229 - 237 2001.2
-
遅延情報を利用した非同期式RTL設計モデルの提案
今井 雅,南谷 崇
電子情報通信学会技術研究報告 VLD2000 ( 92 ) 137 - 142 2000.11
-
2線式ドミノ論理による細粒度パイプライン・データパスの性能比較
今井 雅,南谷 崇
電子情報通信学会技術研究報告 CPSY99 ( 93 ) 73 - 80 1999.11
-
SD符号を用いた非同期式高速除算器
中野栄治,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 CPSY99 ( 9 ) 21 - 28 1999.4
-
Scalable-Delay-Insensitive Design: A high-performance approach to dependable asynchronous systems
Takashi Nanya, Akihiro Takamura, Masashi Kuwako, Masashi Imai, Motokazu Ozawa, Metehan Ozcan, Rafael Morizawa, Hiroshi Nakamura
Proc. International Symposium on Future of Intellectual Integrated Electronics 531 - 540 1999.3
-
符号確定位置を考慮した非同期式SD除算器の設計と評価
中野栄治,今井 雅,中村 宏,南谷 崇
情報処理学会第58会全国大会−講演論文集(1) 51 - 52 1999.3
-
Layout Methodology for SDI Model Asynchronous Circuits
Metehan Ozcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
情報処理学会第58会全国大会−講演論文集(1) 45 - 46 1999.3
-
データの符号化を考慮した非同期式データパスの評価
今井 雅,福田伸樹,中村 宏,南谷 崇
情報処理学会第58回全国大会−講演論文集(1) 47 - 48 1999.3
-
DCVSLを使用した非同期式細粒度パイプライン・データパスの論理合成
今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 CPSY98 47 - 54 1998.9
-
非同期式プロセッサにおける複合演算の効果
今井 雅,中村 宏,南谷 崇
情報処理学会第56回全国大会−講演論文集(1) 139 - 140 1998.3
-
Issues in the floor planning and layout of asynchronous VLSI systems
Metehan Ozcan,今井 雅,中村 宏,南谷 崇
情報処理学会第56回全国大会−講演論文集(1) 127 - 128 1998.3
-
TITAC-2: An asynchronous 32-bit microprocessor
Akihiro Takamura, Masashi Imai, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Masashi Kuwako, Yoichiro Ueno, Takashi Nanya
Proc. ASP-DAC98 319 - 320 1998.2
-
TITAC-2: A 32-bit Asynchnorouns Microprocessor based on Scalable-Delay-Insensitive Model
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
Proc. ICCD97 288 - 294 1997.10
-
TITAC-2: A 32-bit Scalable-Delay-Insensitive Microprocessor
Takashi Nanya, Akihiro Takamura, Masahi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, F. Okamoto, H. Fujimoto, O. Fujita, M. Yamashina, M. Fukuma.
Proc. HOT Chips IX 19 - 32 1997.8
-
配線遅延を考慮した非同期式加算回路の性能評価
今井 雅,南谷 崇
電子情報通信学会技術研究報告 ICD97 9 - 16 1997.4
-
レイアウトデータに基づく非同期式加算回路の性能比較
今井 雅,藤井太郎,上野洋一郎,南谷 崇
情報処理学会第54回全国大会−講演論文集(1) 133 - 134 1997.3
-
非同期式プロセッサTITAC-2のALU構成
藤井太郎,今井 雅,池田吉郎,石田伯仁,西川慎哉,上野洋一郎,南谷 崇
情報処理学会第54回全国大会−講演論文集(1) 97 - 98 1997.3
-
非同期式乗算器の設計と試作
今井 雅,藤井太郎,上野洋一郎,南谷 崇
電子情報通信学会技術研究報告 ICD96 33 - 40 1996.4
-
Concurrent error detection for Asynchronous Circuits using Current Sensing Techniques
Ravi Kishore,今井 雅,南谷 崇
電子情報通信学会春期大会 1996.3
-
BDD表現からの非同期式組合せ回路の構成法
上野洋一郎,今井 雅,南谷 崇
電子情報通信学会技術研究報告 CPSY95 ( 11 ) 1995.4