Papers - Toshiki Kanamoto
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Energy reduction of health monitoring processor by optimizing supply and back-gate voltages with simulated annealing
Seria Kasai, Yamato Ishida, Fumiya Sano, Tomoya Akasaka, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2024 1 - 6 2024.3
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Transmitting coil for uniform magnetic flux density
Tatsumu Mitsuhashi, Toshiki Kanamoto, Koutaro Hachiya, Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2024 1 - 6 2024.3
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Optimal inner diameter of single-layer planar spiral coils
Kotaro Terada, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2024 1 - 6 2024.3
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RESURF Structure optimization of SiC trench MOSFET using machine learning
Tomoya Akasaka, Ichirota Takazawa, Seria Kasai, Atsushi Kurokawa, Toshiki Kanamoto,
Workshop on Synthesis And System Integration of Mixed Information technologies 2024 1 - 6 2024.3
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EMCを考慮したプロセッサ実装基板の設計に関する研究
本田悟, 石田大和, 佐野文也, 葛西瀬梨亜, 松村哲哉, 高澤一朗太, 金本俊幾
情報処理学会東北支部研究報告 2023-7 ( 1-4 ) 1 - 4 2024.2
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Compensation capacitance tunings of wireless power transfer systems using artificial neural network
Kai Sato, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
IEICE Communications Express 2023.12
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LoRa Based Wireless Sensor Network for Bus Tracking System in Contoured Castle Town
Fumiya Sano, Kouki Fukuda, Shinji Kubo, Sumio Tanba, Yamato Ishida, Atsushi Kurokawa, Toshiki Kanamoto
GCCE 224 - 225 2023.10
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LSIの放射性エミッションノイズモデリングに向けたTEG設計
石田大和, 佐野文也, 葛西瀬梨亜, 神谷浩, 松村哲哉, 今村幸祐, 金本俊幾
DAシンポジウム2023 2022-7 ( 5-3 ) 1 - 4 2023.9
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世界自然遺産に設置するための気象・地象・生態系センサノードの 開発
葛西瀬梨亜,石田大和,金本俊幾
弘前大学白神研究会研究報告会 2022-7 ( 5-3 ) 1 - 4 2023.4
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LoRaにおける通信条件
鈴木駿輔,金本俊幾
情報処理学会東北支部研究報告 2022-7 ( 5-3 ) 1 - 4 2023.2
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トレンチ型SiC-MOSFETの素子構造推定
工藤歩華,宗形恒夫
情報処理学会東北支部研究報告 2022-7 ( 5-6 ) 1 - 4 2023.2
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オンチップデカップリング容量の最適化と評価方法の提案
石田大和,宗形恒夫,松村哲哉,金本俊幾
情報処理学会東北支部研究報告 2022-7 ( 5-5 ) 1 - 4 2023.2
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UAVの消費エネルギー低減に向けた評価
上野颯太,金本俊幾
情報処理学会東北支部研究報告 2022-7 ( 5-4 ) 1 - 4 2023.2
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Bayesian Neural Network Based Inductance Calculations of Wireless Power Transfer Systems
Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 2023.2
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A Thermally Optimizing Method of Thin Film Resistor Trimming with Machine Learning
Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 2023.2
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Electronic component placement optimization for heat measures of smartglasses
Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 2023.2
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A Parabolic Spiral Coil Transmitter with Uniform Magnetic Field for Smart Devices
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 20 ( 1 ) 20220492 - 20220492 2022.12
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A Bernoulli Spiral Coil Transmitter for Charging Various Small Electronic Devices
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 19 ( 23 ) 20220419 - 20220419 2022.12
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A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers.
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
GCCE 224 - 225 2022.10
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A thermally optimizing method of thin film resistor trimming with machine learning
Tomoya Akasaka, Shigeru Hidaka, Ryosuke Watanabe, Taisei Arima, Atsushi Kurokawa, and Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2022 1 - 6 2022.10
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Heating of foreign object in inductive wireless charging
Issei Sato, Ryotaro Kudo, Toshiki Kanamoto, Koutaro Hachiya, Shinsuke Kashiwazaki, and Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2022 1 - 6 2022.10
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Electronic component placement optimization for heat measures of smartglasses
Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, and Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2022 1 - 6 2022.10
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Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems.
Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
GCCE 222 - 223 2022.10
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パターン密度均一化に貢献するオンチップデカップリング容量セルの提案
岡巧, 葛西瀬梨亜, 石田大和, 佐野文也, 今井雅, 金本俊幾
DAシンポジウム2022 88 - 92 2022.9
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Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules.
Ryosuke Watanabe, Shigeru Hidaka, Tomoya Akasaka, Shota Kajiya, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto
MWSCAS 1 - 4 2022.8
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磁界結合型ワイヤレス電力伝送システムにおける異物の発熱
佐藤一世, 金本俊幾, 黒川敦
電気学会 全国大会 講演論文集 1 - 4 2022.3
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リング状容量性カプラを用いた電力伝送システムの特性解析
柏崎晋助, 金本俊幾, 黒川敦
電気学会 全国大会 講演論文集 1 - 4 2022.3
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複数装置を充電可能な放物螺旋コイルの送電機
工藤遼太朗, 金本俊幾, 黒川敦
電気学会 全国大会 講演論文集 1 - 4 2022.3
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オンチップインピーダンスのモデリング
佐野文也,金本俊幾
情報処理学会東北支部研究報告 2021-6 ( 5-4 ) 1 - 4 2022.2
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ドローンの動作最適化による消費エネルギーの低減
武田朋弥,丹波澄雄,藤崎和弘,金本俊幾
情報処理学会東北支部研究報告 2021-6 ( 5-1 ) 1 - 4 2022.2
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薄膜抵抗器のトリミング形状に対する機械学習 を用いた熱的最適化
赤坂知哉,梶谷翔太,渡邊良祐,有馬大生,金本俊幾
情報処理学会東北支部研究報告 2021-6 ( 5-2 ) 1 - 4 2022.2
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低消費エネルギープロセッサのSoC物理設計
葛西瀬梨亜,畠山寛,今井雅,黒川敦,金本俊幾
情報処理学会東北支部研究報告 2021-6 ( 5-3 ) 1 - 4 2022.2
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Receiver coil built into belt for heat dissipation of watch-type smart devices
Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
IEICE Electronics Express 19 ( 3 ) 20210497 - 20210497 2022.2
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Planar Single-Coil Transmitters for Efficiently Charging Smart Devices of Various Receiving Coil Sizes
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
the International Conference on Emerging Technologies for Communications(ICETC) 68 1 - 5 2021.12
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An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring
Toshiki Kanamoto, Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara
the IEEE Global Conference on Consumer Electronics(GCCE) 1 - 2 2021.11
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Energy efficient RISC-V processor for portable sensor applications
Kan Hatakeyama, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Imai, Atsushi Kurokawa, and Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2021 1 - 4 2021.3
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Using receiver coils for dissipating heat of watch-type smart devices
Shinsuke Kashiwazaki, Kodai Matsuhashi, Motoki Ishizaki, Toshiki Kanamoto, Koutaro Hachiya, Ryosuke Watanabe, and Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2021 1 - 6 2021.3
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Thermal design technology for non-low power hearables
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2021 1 - 6 2021.3
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Thermally optimization of the trimming shape of thin film NiCr resistors to improve pulse durability
Ryosuke Watanabe, Keita Izawa, Shota Kajiya, Tomohiro Aoba, Ryo Arima, Atsushi Kurokawa, and Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2021 1 - 6 2021.3
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Effective methods to promote heat dissipation of wrist wearables
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa
IEICE Electronics Express 18 ( 5 ) 20210017 - 20210017 2021.3
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ヒアラブルデバイスの熱回路モデルと解析
松橋功大,今井雅,金本俊幾,黒川敦,
情報処理学会東北支部研究報告 2020-6 ( 2-1 ) 1 - 4 2021.2
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LSI・パッケージ・ボード協調設計に向けたオンチップインピーダンス抽出
岡巧,黒川敦,今井雅,金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-4 ) 1 - 4 2021.2
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TOFカメラを用いた魚体重推定
及川大樹,野村哲哉,丹波澄雄,黒川敦,今井雅,金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-3 ) 1 - 4 2021.2
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耐パルス性NiCr薄膜抵抗器のトリミング形状に対する熱的最適化
有馬諒,梶谷翔太,伊澤敬太,渡邊良祐,青葉智寛,黒川敦,今井雅,金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-2 ) 1 - 4 2021.2
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データシートを用いたトレンチ型IGBTの素子構造推定
有馬大生,宗形恒夫,黒川敦,今井雅,金本俊幾
情報処理学会東北支部研究報告 2020-6 ( 1-1 ) 1 - 4 2021.2
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A Virtual Optical Holographic Encryption System Using Expanded Diffie-Hellman Algorithm
Yang Peng, Tomoyuki Nagase, Toshiki Kanamoto, Tsutomu Zeniya, Shan You
IEEE Access 9 22071 - 2077 2021.2
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A VOHE System for Underwater Communications
Yang Peng, Tomoyuki Nagase, Shan You, Toshiki Kanamoto
Electronics 9 ( 10 ) 1557 - 1557 2020.9
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A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis
Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai
IEICE Electronics Express 17 ( 14 ) 20200198 - 20200198 2020.7
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An Optical Encryption Digital Holographic System Based on RSA Algorithm
Yang Peng, Tomoyuki Nagase and Toshiki Kanamoto
INFORMATION Vol.23 ( No.2 ) 139 - 148 2020.6
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Effective thermal modeling of a thin film snubber resistor for power modules
Ryosuke Watanabe, Keita Izawa, Shota Kajiya, Daiki Tsunemoto, Koki Kasai, Atsushi Kurokawa, Toshiki Kanamoto
Nonlinear Theory and Its Applications, IEICE 11 ( 2 ) 253 - 266 2020.4
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Thermal Model and Countermeasures for Future Smart Glasses
Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa
Sensors 20 ( 5 ) 1 - 20 2020.3
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メンテナンスフリーセンサーノード実現に向けた画像分析と消費電力低減の検討
畑瀬拓実, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-3 ) 1 - 3 2020.2
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シミュレーションベースオンチップ電源容量抽出手法
葛西孝己,今井 雅, 黒川 敦, 金本 俊幾
情報処理学会東北支部研究報告 2019-6 ( 1-1 ) 1 - 6 2020.2
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パワーフィルム抵抗器のパルス破壊解析に向けた熱回路モデルの検討
常本大貴, 梶谷翔太, 伊澤敬汰, 渡邊良祐, 葛西孝己, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 1-2 ) 1 - 5 2020.2
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耐パルス性薄膜抵抗器の有限要素法構造モデルの作成
梶谷翔太, 伊澤敬汰, 常本大貴, 葛西孝己, 黒川敦, 金本俊幾, 渡邊良祐
情報処理学会東北支部研究報告 2019-6 ( 1-3 ) 1 - 4 2020.2
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パワーモジュールの熱応力連成解析に向けたIGBT等価回路モデルの検討
伊藤颯汰, 宗形恒夫, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-1 ) 1 - 4 2020.2
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LPWA通信規格LoRaを用いたセンサノードの低消費電力通信の評価
畠山寛, 丹波澄雄, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-2 ) 1 - 4 2020.2
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Thermal placement on PCB of components including 3D ICs
Satomi Yuuta, Hachiya Koutaro, Kanamoto Toshiki, Watanabe Ryosuke, Kurokawa Atsushi
IEICE Electronics Express 17 ( 3 ) 20190737 - 20190737 2020.1
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Thermal placement on PCB of components including 3D ICs
Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
IEICE Electronics Express 17 ( 3 ) 20190737 - 20190737 2020.1
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Thermal Resistance Model and Analysis for Future Smart Glasses
K.Matsuhashi, T.Kanamoto, A.Kurokawa
International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) 14 2019.10
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Thermal modeling and simulation of a smart wrist-worn wearable device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Workshop on Synthesis And System Integration of Mixed Information technologies 2019 138 - 143 2019.10
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Efficiency investigation of capacitors mounted on re-distribution layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, and Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2019 176 - 179 2019.10
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Quantitative performance comparison of asynchronous and synchronous comparator
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Workshop on Synthesis And System Integration of Mixed Information technologies 2019 296 - 297 2019.10
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An efficient thermal model of thin film NiCr resistors considering pulse response
Ryosuke Watanabe, Keita Izawa, Shota Kajiya, Taiki Tsunemoto, Koki Kasai, Atsushi Kurokawa, Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies 2019 164 - 167 2019.10
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An Efficient Thermal Model of Thin Film NiCr Resistors Considering Pulse Response
Ryosuke Watanabe, Keita Izawa, Shota Kajiya, Taiki Tsunemoto, Koki Kasai, Atsushi Kurokawa, Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies, SASIMI 164 - 167 2019.10
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Thermal Resistance Model and Analysis for Future Smart Glasses
Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa
International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 1 - 4 2019.10
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Thermal Modeling and Simulation of a Smart Wrist-Worn Wearable Device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masasi Imai, Atsushi Kurokawa
138 - 143 2019.10
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Quantitative Performance Comparison of Asynchronous and Synchronous Comparator
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Workshop on Synthesis And System Integration of Mixed Information technologies, SASIMI 296 - 297 2019.10
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Efficiency Investigation of Capacitors Mounted on Re-Distribution Layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
Workshop on Synthesis And System Integration of Mixed Information technologies, SASIMI 176 - 179 2019.10
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A Multicore Chip Load Model for PDN Analysis Considering Voltage–Current-Timing Interdependency and Operation Mode Transitions
Toshiki Kanamoto
IEEE Transactions on Components, Packaging and Manufacturing Technology 9 ( 9 ) 1669 - 1679 2019.9
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A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
IEEE International Midwest Symposium on Circuits and Systems, MWCAS 62 1085 - 1088 2019.8
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Hardware Trojan Insertion and Detection in Asynchronous Circuits
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019 25 134 - 143 2019.5
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Neural network-based 3D IC interconnect capacitance extraction
R. Kasai, T. Kanamoto, M. Imai, A. Kurokawa, K. Hachiya
International Conference on Communication Engineering and Technology (ICCET) 2 168 - 172 2019.4
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Neural Network-Based 3D IC Interconnect Capacitance Extraction
Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
2019 2nd International Conference on Communication Engineering and Technology (ICCET 2019) 168 - 172 2019.4
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リストウェアラブルデバイスのベルト放熱効果
岡本慎太郎, 松橋功大, 今井雅, 金本俊幾, 黒川敦
電気学会 全国大会 講演論文集 32 2019.3
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リストウェアラブルデバイスのベルト放熱効果
岡本慎太郎, 松橋功大, 今井雅, 金本俊幾, 黒川敦
電気学会全国大会講演論文集(CD-ROM) 2019 ROMBUNNO.3‐025 2019.3
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束データ方式非同期式回路におけるハードウェアトロイ検出手法の評価
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B4-3 ) 2019.2
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ハードウェアトロイ無効化のための多重化システムの実装
和島純也, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B4-2 ) 2019.2
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遅延ばらつきを考慮した遅延線設計による束データ方式非同期式回路の高性能化
赤坂親一郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2018-9 ( B4-1 ) 2019.2
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AC解析を用いたオンチップ電源分配網の容量抽出手法
葛西孝己,黒川 敦, 今井 雅, 金本 俊幾
情報処理学会東北支部研究報告 2018-9 ( B4-4 ) 2019.2
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AC解析を用いたオンチップ電源分配網の容量抽出手法
葛西孝己, 黒川敦, 今井雅, 金本俊幾
情報処理学会 東北支部研究会 2019.2
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遅延ばらつきを考慮した遅延線設計による束データ方式非同期式回路の高性能化
赤坂親一郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会 東北支部研究会 2019.2
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束データ方式非同期式回路におけるハードウェアトロイ検出手法の評価
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
情報処理学会 東北支部研究会 2019.2
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ハードウェアトロイ無効化のための多重化システムの実装
和島純也, 金本俊幾, 黒川敦, 今井雅
情報処理学会 東北支部研究会 2019.2
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束データ方式非同期式回路におけるハードウェアトロイ攻撃と対策
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会ハードウェアセキュリティフォーラム 2018.12
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Optimization of full-chip power distribution networks in 3D ICs
Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, and Atsushi Kurokawa
International Conference on Integrated Circuits and Microsystems (ICICM) 134 - 138 2018.11
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Variability in Thermo-mechanical Stress Applied to the Bonding Junction of Power MOSFET
Toshiki Kanamoto, Kazuaki Nomiya, Koki Kasai, Atsushi Kurokawa, Masashi Imai, Tsuneo Munakata
11th ACM/IEEE Workshop on Variability Modeling and Characterization (VMC) 1 - 2 2018.11
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2phaseハンドシェイクプロトコルに基づく束データ方式非同期式回路のレプリカ遅延線設計
赤坂親一郎, 金本俊幾, 黒川敦, 今井雅
DAシンポジウム2018論文集 93 - 98 2018.8
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FOWLPを⽤いたLSIにおける再配線層上キャパシタおよびオンチップ容量の最適化
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始
DAシンポジウム2018論文集 88 - 92 2018.8
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Impact of mutual inductance on timing in nano-scale SoC
Sakata Kazuyuki, Hasegawa Takashi, Ichikawa Kouji, Kanamoto Toshiki
IEICE Electronics Express 15 ( 11 ) 20180376 - 20180376 2018.6
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Impact of mutual inductance on timing in nano-scale SoC
Kazuyuki Sakata, Takashi Hasegawa, Kouji Ichikawa, Toshiki Kanamoto
IEICE Electronics Express 15 ( 11 ) 2018.6
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An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency Between Supply Voltage, Current Profile and Clock Latency
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
2018 IEEE 22th Workshop on Signal and Power Integrity (SPI) 1 - 4 2018.5
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Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
The 21st Workshop on Synthesis And System Integration of Mixed Information technologies R4-19 1 - 6 2018.3
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Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Yuuta Satomi, Koutaro Hachiya, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, Atsushi Kurokawa
The 21st Workshop on Synthesis And System Integration of Mixed Information technologies R2-10 1 - 6 2018.3
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Prediction of the impact of Mutual Inductance on Timing Towards Nano-scale SoC
Kazuyuki Sakata, Takashi Hasegawa, kouji Ichikawa, Toshiki Kanamoto
The 21st Workshop on Synthesis And System Integration of Mixed Information technologies R1-8 1 - 3 2018.3
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モバイル機器向け３D-ICの放熱促進方法
松橋功大，古見薫，今井雅，岡本慎太郎，金本俊幾，里見優太，黒川敦
電気学会 全国大会 講演論文集 2018 2018.3
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ビザンチンフォールトトレラントシステムの構築と実用性評価
七尾健, 石川雄大, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2017-6 ( B3-2 ) 2018.2
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容量素子最適化のための LSI・パッケージ・ボード電源網解析モデルの構築
葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2017-6 ( B1-1 ) 2018.2
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PowerMOS デバイス熱設計のためのボンディングワイヤモデルの構築
太田拓磨, 宗形恒夫, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2017-6 ( B1-2 ) 2018.2
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CMOS回路における消費エネルギー低減のための電源電圧と閾値電圧の調節手法
成田全, 葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2017-6 ( B1-3 ) 2018.2
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FPGA の信号伝搬遅延の温度依存性に関する研究
江良祥耶, 葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2017-6 ( B1-4 ) 2018.2
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ランダム遅延素子を用いた耐タンパ非同期式回路の設計
豊嶋太樹, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2017-6 ( B3-1 ) 2018.2
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Thermal-Aware Tile-Based Block Placement for 3D ICs
Ryosuke Hatsuta, Masashi Imai, Toshiki Kanamoto, Shintaro Okamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session 1B07 2017.8
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Constructing a LPB Model for Capacitance Optimization
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2E09 ( 0 ) 201 - 201 2017.8
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Constructing a Bond-Wire Model for Thermal design of Power Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2E03 ( 0 ) 196 - 196 2017.8
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A Study on Asyncronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1G04 ( 0 ) 94 - 94 2017.8
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Estimating Walking State When Holding Object in Hand by Using Neural Network
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2B19 ( 0 ) 165 - 165 2017.8
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Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B17 ( 0 ) 28 - 28 2017.8
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Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B16 ( 0 ) 27 - 27 2017.8
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Reducing Temperature by Relocating 3D IC Structures
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B15 ( 0 ) 26 - 26 2017.8
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A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B10 ( 0 ) 21 - 21 2017.8
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Hardware Trojan Comparison between Synchronous and Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B08 ( 0 ) 19 - 19 2017.8
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Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B06 ( 0 ) 17 - 17 2017.8
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LSI-Package-Board Power Delivery Network Modeling for Capacitor Placement Optimization at 15nm Node
2017 111 - 114 2017.8
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Reliabilty Analysis of Multi-core System using the Markov model.
Kotaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IEICE A-7-1 - 82 2017.3
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A Study on Minimizing Energy Consunption in Ultra-Low Voltage Circuits
Kentaro Taki, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of low noise asynchronous circuit by handshake circuit multiplexing
Tatsuya Ishikawa, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of High Performance Asynchronous Circuit Under Ultra Low Voltage Environment
Ryuhei Tachika, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Experimental Evaluation of FPGAsPerformance Variation using Multistage Ring Oscillator
Komei Masukawa, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Thermal-Aware Tile-Based Block Placement for 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 18 - 18 2017
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Accurate prediction of interconnect capacitance in Self-Aligned Quadruple Patterning
T. Kanamoto, H. Ammo, T. Hasegawa, S. Kobayashi, T. Fukuda and M. Kawano
2016 IEEE 20th Workshop on 2016 IEEE 20th Workshop 2016.5
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A new EMI-noise reduction method in LSI-Package-Board system
Takashi Hasegawa, Toshiki Kanamoto, Hiroaki Ammo, Masaharu Kawano, Toshikazu Fukuda, Sachiko Kobayashi, Atsushi Kurokawa
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) 2016.5
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Structure optimization for timing in nano scale FinFET
Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 12 ( 9 ) 2015.5
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Structure optimization for timing in nano scale FinFET
Kanamoto Toshiki, Akamine Takeichiro, Ammo Hiroaki, Hasegawa Takashi, Shimizu Kouhei, Kumano Yoshinori, Kawano Masaharu, Kurokawa Atsushi
IEICE Electron. Express 12 ( 9 ) 20150297 - 20150297 2015.4
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Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Kanamoto Toshiki, Inaba Hisato, Chiba Toshiharu, Ogasahara Yasuhiro
IEICE Electron. Express 11 ( 3 ) 20130813 - 20130813 2014.4
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Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Toshiki Kanamoto, Hisato Inaba, Toshiharu Chiba, Yasuhiro Ogasahara
IEICE ELECTRONICS EXPRESS 11 ( 3 ) 2014
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Supply Noise Suppression by Triple-Well Structure
Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 ( 4 ) 781 - 785 2013.4
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Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
Takashi Saito, Akihiro Tanaka, Takuro Hayashi, Hideyuki Kikuchihara, Toshiki Kanamoto, Hiroo Masuda, Masataka Miyake, Shuhei Amakawa, Hans J. Mattausch, Michiko Miura-Mattausch
JAPANESE JOURNAL OF APPLIED PHYSICS 50 ( 4 ) 2011.4
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A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
Takashi Saito, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A ( 9 ) 1605 - 1611 2010.9
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Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 8 ) 1349 - 1358 2010.8
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Impact of Self-Heating in Wire Interconnection on Timing
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 3 ) 388 - 392 2010.3
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Interconnect Modeling: A Physical Design Perspective
Atsushi Kurokawa, Takashi Sato, Toshiki Kanamoto, Masanori Hashimoto
IEEE TRANSACTIONS ON ELECTRON DEVICES 56 ( 9 ) 1840 - 1851 2009.9
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An approach for reducing leakage current variation due to manufacturing variability
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3016 - 3023 2009
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Improvement in computational accuracy of output transition time variation considering threshold voltage variations
Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 4 ) 990 - 997 2009
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Impact of Well Edge Proximity Effect on Timing
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3461 - 3464 2008.12
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A parallel method to extract critical areas of net pairs for diagnosing bridge faults
Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3524 - 3530 2008
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Method of extracting pairs of adjacent wires for diagnosing bridging faults based on IDDQ testing
末光啓一, 伊藤俊明, 金本俊幾, 寺井正幸, 小谷憲, 澤田茂穂
情報処理学会シンポジウム論文集 2007 ( 7 ) 215 - 220 2007.8
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A fast characterizing method for large embedded memory modules on SoC
Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E90A ( 4 ) 815 - 822 2007.4
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Impact of intrinsic parasitic extraction errors on timing and noise estimation
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kbayashi, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3666 - 3670 2006.12
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006.12
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Formula-based method for capacitance extraction of interconnects with dummy fills
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 847 - 855 2006
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
10th IEEE Workshop on Signal Propagation on Interconnects, Proceedings 227 - 230 2006
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A method of precise estimation of physical parameters in LSI interconnect structures
T Kanamoto, T Watanabe, M Shirota, M Terai, T Kunikiyo, K Ishikawa, Y Ajioka, Y Horiba
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3463 - 3470 2005.12
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Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills
A Kurokawa, T Kanamoto, T Ibe, A Kasebe, WF Chang, T Kage, Y Inoue, H Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3471 - 3478 2005.12
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A practical approach for efficiently extracting interconnect capacitances with floating dummy fills
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Indoe, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 11 ) 3180 - 3186 2005
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Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
T Kunikiyo, T Watanabe, T Kanamoto, H Asazato, M Shirota, K Eikyu, Y Ajioka, H Makino, K Ishikawa, S Iwade, Y Inoue
IEEE TRANSACTIONS ON ELECTRON DEVICES 51 ( 5 ) 726 - 735 2004.5
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D30V/MPEG multimedia processor
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
IEEE Micro 19 38 - 47 1999.7