Papers - KUROKAWA Atsushi
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45-65nmノードにおける遅延ばらつき特性の環境温度依存性
中林太美世, 黒川敦, 佐藤高史, 橋本昌宜, 増田弘生
電子情報通信学会 第20回 回路とシステム軽井沢ワークショップ 論文集 691 - 696 2007.4
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信頼性保証のためのNBTIのモデリングとシミュレーション方法
黒川敦, 大嶋潔, 木村安行, 宮下博之, 日隈裕洋, 北爪和俊, 伊部哲也
電子情報通信学会 第20回 回路とシステム軽井沢ワークショップ 論文集 13 - 18 2007.4
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クリスタル発振回路に起因するEMIノイズの解析とチップ内対策
黒川敦, 藤田浩志, 伊部哲也, 渡辺徹
電子情報通信学会 第20回 回路とシステム軽井沢ワークショップ 論文集 475 - 480 2007.4
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バラツキのモデリング技術 （招待講演）
黒川敦
電子情報技術産業協会 EDS Fair システム・デザイン・フォーラム 2007 2007.1
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Impact of intrinsic parasitic extraction errors on timing and noise estimation
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3666 - 3670 2006.12
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A gate delay model focusing on current fluctuation over wide-range of process and environmental variability
Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
Proceedings of ACM/IEEE International Workshop on Timing Issues (ICCAD 2006) 47 - 53 2006.11
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Calculating the effective capacitance for interconnect loads based on Thevenin model
Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, and Yasuaki
Proceedings 2006 International Conference on Communications, Circuits and Systems (ICCCAS) 2474 - 2477 2006.6
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Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay
Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 840 - 846 2006.4
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Determination of interconnect structural parameters for best- and worst-case delays
Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 856 - 864 2006.4
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Formula-based method for capacitance extraction of interconnects with dummy fills
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 847 - 855 2006.4
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電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル
新開健一, 橋本昌宜, 黒川敦, 尾上孝雄
電子情報通信学会 第19回 回路とシステム軽井沢ワークショップ 論文集 559 - 564 2006.4
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Calculating the effective capacitance for interconnect loads based on Thevenin model
Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, and Yasuaki Inoue
電子情報通信学会 第19回 回路とシステム軽井沢ワークショップ 論文集 1 - 4 2006.4
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A gate delay model focusing on current fluctuation over wide-range of process and environmental variability
Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2006) 59 - 64 2006.2
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Gate-current model for advanced MOSFET technologies implemented into HiSIM2
R.Inagaki, N.Sadachika, K.Konno, D.Navarro, K.Machida, Q.Ngo, C.Y.Yang, A.Kurokawa, T.Ezaki, H.J.Mattausch, M.Miura-Mattausch, Y.Inoue
Gate-current model for advanced MOSFET technologies implemented into HiSIM2 43 - 46 2006.1
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Efficient large scale integration power/ground network optimization based on grid genetic algorithm
Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 12 ) 3412 - 3420 2005.12
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Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills
Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Testuro Kage, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 12 ) 3471 - 3478 2005.12
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Second-order polynomial expressions for on-chip interconnect capacitance
Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 12 ) 3453 - 3462 2005.12
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Modeling the effective capacitance of interconnect loads for predicting CMOS gate slew
Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 12 ) 3367 - 3374 2005.12
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A practical approach for efficiently extracting interconnect capacitances with floating dummy fills
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 11 ) 3180 - 3187 2005.11
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A novel model for computing the effective capacitance of CMOS gates with interconnect loads
Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 10 ) 2562 - 2569 2005.10