Papers - KUROKAWA Atsushi
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Modeling and analysis for predicting clock skew of stacked chips
Seira Kamiie, Toshiki Kanamoto, Masashi Imai, Shintaro Okamoto, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Thermal-aware tile-based block placement for 3D ICs
Ryosuke Hatsuta, Masashi Imai, Toshiki Kanamoto, Shintaro Okamoto, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Reducing temperature by relocating 3D IC structures
Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Optimizing power distribution network using multi-objective genetic algorithm
Yuuta Satomi, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Method for mitigating heat of 3D stacked memory for small electronic devices
Shintaro Okamoto, Kaoru Furumi, Masashi Imai, Toshiki Kanamoto, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Estimating walking state when holding object in hand by using neural network
Ryo Sasaki, Toshiki Kanamoto, Masashi Imai, Kaoru Furumi, and Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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A study on replica delay circuit of bundled-data transfer asynchronous circuits
Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, and Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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Hardware Trojan comparison between synchronous and asynchronous circuits
Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, and Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2017.8
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容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築
葛西孝己，今井雅，黒川敦，金本俊幾，陳俊，橋本昌宜，神藤始
電気関係学会 東北支部連合大会 講演論文集 2017.8
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PowerMOSデバイス熱設計のためのボンディングワイヤモデルの構築
太田拓磨，葛西孝己，今井雅，黒川敦，金本俊幾，宗形恒夫
電気関係学会 東北支部連合大会 講演論文集 2017.8
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マルチコアシステムのマルコフモデルによる信頼性評価
和島純也, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会 総合大会 D-10-3 2017.3
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非同期式NoCルータへのハードウェアトロイ挿入に関する研究
稲葉光太郎, 金本俊幾, 黒川敦, 今井雅
電子情報通信学会 総合大会 A-7-1 2017.3
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Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs
Kaoru Furumi, Masashi Imai, and Atsushi Kurokawa
International Symposium on Quality Electronic Design 2017.3
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数百層積層メモリにおける各パラメータの温度への影響
岡本慎太郎, 黒川敦
情報処理学会 東北支部研究会 1 - 4 2017.2
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Random delay elements for tamper resistant asynchronous circuits based on 2-phase handshaking protocol
Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, and Masashi Imai
Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 113 - 118 2016.10
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チップ外周熱伝導壁による三次元集積回路の温度低減
古見薫, 新岡七奈子, 岡本慎太郎, 今井雅, 黒川敦
電子情報通信学会 ソサエティ大会 講演論文集 A-6-4 2016.9
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A study on byzantine fault tolerant systems using SCore cluster system software
Takeru Nanao，Atsushi Kurokawa, and Masashi Imai
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 2A07 2016.8
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Recognition of wrist position while walking by using wearable triaxial accelerometers
◦Kaoru Furumi, Shintaro Mizoguchi, Nanako Niioka, Masashi Imai, and Atsushi Kurokawa
Proc. of the International Technical Conference on Circuits/Systems, Computers and Communications 97 - 100 2016.7
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マルチソースバッファを用いた積層チップのクロック分配方法
新岡七奈子, 今井雅, 古見薫, 黒川敦
電子情報通信学会 技術研究報告 116 ( 94 ) 167 - 172 2016.6
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ランダム遅延素子を用いた耐タンパ非同期式パイプライン回路
豊嶋太樹, 黒川敦, 今井雅
電子情報通信学会 技術研究報告 116 ( 94 ) 185 - 190 2016.6