Papers - Toshiki Kanamoto
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FPGA の信号伝搬遅延の温度依存性に関する研究
江良祥耶, 葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2017-6 ( B1-4 ) 2018.2
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ランダム遅延素子を用いた耐タンパ非同期式回路の設計
豊嶋太樹, 金本俊幾, 黒川敦, 今井雅
情報処理学会東北支部研究報告 2017-6 ( B3-1 ) 2018.2
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Thermal-Aware Tile-Based Block Placement for 3D ICs
Ryosuke Hatsuta, Masashi Imai, Toshiki Kanamoto, Shintaro Okamoto, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session 1B07 2017.8
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Constructing a LPB Model for Capacitance Optimization
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2E09 ( 0 ) 201 - 201 2017.8
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Constructing a Bond-Wire Model for Thermal design of Power Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2E03 ( 0 ) 196 - 196 2017.8
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A Study on Asyncronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1G04 ( 0 ) 94 - 94 2017.8
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Estimating Walking State When Holding Object in Hand by Using Neural Network
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2B19 ( 0 ) 165 - 165 2017.8
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Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B17 ( 0 ) 28 - 28 2017.8
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Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B16 ( 0 ) 27 - 27 2017.8
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Reducing Temperature by Relocating 3D IC Structures
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B15 ( 0 ) 26 - 26 2017.8
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A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B10 ( 0 ) 21 - 21 2017.8
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Hardware Trojan Comparison between Synchronous and Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B08 ( 0 ) 19 - 19 2017.8
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Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B06 ( 0 ) 17 - 17 2017.8
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LSI-Package-Board Power Delivery Network Modeling for Capacitor Placement Optimization at 15nm Node
2017 111 - 114 2017.8
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Reliabilty Analysis of Multi-core System using the Markov model.
Kotaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IEICE A-7-1 - 82 2017.3
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A Study on Minimizing Energy Consunption in Ultra-Low Voltage Circuits
Kentaro Taki, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of low noise asynchronous circuit by handshake circuit multiplexing
Tatsuya Ishikawa, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of High Performance Asynchronous Circuit Under Ultra Low Voltage Environment
Ryuhei Tachika, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Experimental Evaluation of FPGAsPerformance Variation using Multistage Ring Oscillator
Komei Masukawa, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Thermal-Aware Tile-Based Block Placement for 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 18 - 18 2017