Papers - Toshiki Kanamoto
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Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
Takashi Saito, Akihiro Tanaka, Takuro Hayashi, Hideyuki Kikuchihara, Toshiki Kanamoto, Hiroo Masuda, Masataka Miyake, Shuhei Amakawa, Hans J. Mattausch, Michiko Miura-Mattausch
JAPANESE JOURNAL OF APPLIED PHYSICS 50 ( 4 ) 2011.4
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A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
Takashi Saito, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A ( 9 ) 1605 - 1611 2010.9
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Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 8 ) 1349 - 1358 2010.8
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Impact of Self-Heating in Wire Interconnection on Timing
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 3 ) 388 - 392 2010.3
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Interconnect Modeling: A Physical Design Perspective
Atsushi Kurokawa, Takashi Sato, Toshiki Kanamoto, Masanori Hashimoto
IEEE TRANSACTIONS ON ELECTRON DEVICES 56 ( 9 ) 1840 - 1851 2009.9
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Improvement in computational accuracy of output transition time variation considering threshold voltage variations
Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 4 ) 990 - 997 2009
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An approach for reducing leakage current variation due to manufacturing variability
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3016 - 3023 2009
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Impact of Well Edge Proximity Effect on Timing
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3461 - 3464 2008.12
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A parallel method to extract critical areas of net pairs for diagnosing bridge faults
Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3524 - 3530 2008
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Method of extracting pairs of adjacent wires for diagnosing bridging faults based on IDDQ testing
末光啓一, 伊藤俊明, 金本俊幾, 寺井正幸, 小谷憲, 澤田茂穂
情報処理学会シンポジウム論文集 2007 ( 7 ) 215 - 220 2007.8
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A fast characterizing method for large embedded memory modules on SoC
Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E90A ( 4 ) 815 - 822 2007.4
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Impact of intrinsic parasitic extraction errors on timing and noise estimation
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kbayashi, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3666 - 3670 2006.12
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006.12
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Formula-based method for capacitance extraction of interconnects with dummy fills
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 847 - 855 2006
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
10th IEEE Workshop on Signal Propagation on Interconnects, Proceedings 227 - 230 2006
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A method of precise estimation of physical parameters in LSI interconnect structures
T Kanamoto, T Watanabe, M Shirota, M Terai, T Kunikiyo, K Ishikawa, Y Ajioka, Y Horiba
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3463 - 3470 2005.12
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Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills
A Kurokawa, T Kanamoto, T Ibe, A Kasebe, WF Chang, T Kage, Y Inoue, H Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3471 - 3478 2005.12
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A practical approach for efficiently extracting interconnect capacitances with floating dummy fills
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Indoe, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 11 ) 3180 - 3186 2005
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Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
T Kunikiyo, T Watanabe, T Kanamoto, H Asazato, M Shirota, K Eikyu, Y Ajioka, H Makino, K Ishikawa, S Iwade, Y Inoue
IEEE TRANSACTIONS ON ELECTRON DEVICES 51 ( 5 ) 726 - 735 2004.5
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D30V/MPEG multimedia processor
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
IEEE Micro 19 38 - 47 1999.7