Papers - Toshiki Kanamoto
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Formula-based method for capacitance extraction of interconnects with dummy fills
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 847 - 855 2006
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
10th IEEE Workshop on Signal Propagation on Interconnects, Proceedings 227 - 230 2006
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A method of precise estimation of physical parameters in LSI interconnect structures
T Kanamoto, T Watanabe, M Shirota, M Terai, T Kunikiyo, K Ishikawa, Y Ajioka, Y Horiba
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3463 - 3470 2005.12
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Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills
A Kurokawa, T Kanamoto, T Ibe, A Kasebe, WF Chang, T Kage, Y Inoue, H Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 12 ) 3471 - 3478 2005.12
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A practical approach for efficiently extracting interconnect capacitances with floating dummy fills
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Indoe, Hiroo Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 11 ) 3180 - 3186 2005
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Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
T Kunikiyo, T Watanabe, T Kanamoto, H Asazato, M Shirota, K Eikyu, Y Ajioka, H Makino, K Ishikawa, S Iwade, Y Inoue
IEEE TRANSACTIONS ON ELECTRON DEVICES 51 ( 5 ) 726 - 735 2004.5
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D30V/MPEG multimedia processor
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
IEEE Micro 19 38 - 47 1999.7