Papers - Toshiki Kanamoto
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Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B17 ( 0 ) 28 - 28 2017.8
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Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B16 ( 0 ) 27 - 27 2017.8
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Reducing Temperature by Relocating 3D IC Structures
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B15 ( 0 ) 26 - 26 2017.8
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A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B10 ( 0 ) 21 - 21 2017.8
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Hardware Trojan Comparison between Synchronous and Asynchronous Circuits
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B08 ( 0 ) 19 - 19 2017.8
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Modeling and Analysis for Predicting Clock Skew of Stacked Chips
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 1B06 ( 0 ) 17 - 17 2017.8
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LSI-Package-Board Power Delivery Network Modeling for Capacitor Placement Optimization at 15nm Node
2017 111 - 114 2017.8
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Reliabilty Analysis of Multi-core System using the Markov model.
Kotaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
IEICE A-7-1 - 82 2017.3
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A Study on Minimizing Energy Consunption in Ultra-Low Voltage Circuits
Kentaro Taki, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of low noise asynchronous circuit by handshake circuit multiplexing
Tatsuya Ishikawa, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Realization of High Performance Asynchronous Circuit Under Ultra Low Voltage Environment
Ryuhei Tachika, Toshiki Kanamoto, Masashi Imai
2017 6th IPSJ Tohoku section Workshop 2017.2
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Experimental Evaluation of FPGAsPerformance Variation using Multistage Ring Oscillator
Komei Masukawa, Masashi Imai, Toshiki Kanamoto
2017 6th IPSJ Tohoku section Workshop 2017.2
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Thermal-Aware Tile-Based Block Placement for 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2017 ( 0 ) 18 - 18 2017
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Accurate prediction of interconnect capacitance in Self-Aligned Quadruple Patterning
T. Kanamoto, H. Ammo, T. Hasegawa, S. Kobayashi, T. Fukuda and M. Kawano
2016 IEEE 20th Workshop on 2016 IEEE 20th Workshop 2016.5
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A new EMI-noise reduction method in LSI-Package-Board system
Takashi Hasegawa, Toshiki Kanamoto, Hiroaki Ammo, Masaharu Kawano, Toshikazu Fukuda, Sachiko Kobayashi, Atsushi Kurokawa
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) 2016.5
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Structure optimization for timing in nano scale FinFET
Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 12 ( 9 ) 2015.5
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Structure optimization for timing in nano scale FinFET
Kanamoto Toshiki, Akamine Takeichiro, Ammo Hiroaki, Hasegawa Takashi, Shimizu Kouhei, Kumano Yoshinori, Kawano Masaharu, Kurokawa Atsushi
IEICE Electron. Express 12 ( 9 ) 20150297 - 20150297 2015.4
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Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Kanamoto Toshiki, Inaba Hisato, Chiba Toshiharu, Ogasahara Yasuhiro
IEICE Electron. Express 11 ( 3 ) 20130813 - 20130813 2014.4
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Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Toshiki Kanamoto, Hisato Inaba, Toshiharu Chiba, Yasuhiro Ogasahara
IEICE ELECTRONICS EXPRESS 11 ( 3 ) 2014
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Supply Noise Suppression by Triple-Well Structure
Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 ( 4 ) 781 - 785 2013.4