Papers - Toshiki Kanamoto
-
Accurate prediction of interconnect capacitance in Self-Aligned Quadruple Patterning
T. Kanamoto, H. Ammo, T. Hasegawa, S. Kobayashi, T. Fukuda and M. Kawano
2016 IEEE 20th Workshop on 2016 IEEE 20th Workshop 2016.5
-
A new EMI-noise reduction method in LSI-Package-Board system
Takashi Hasegawa, Toshiki Kanamoto, Hiroaki Ammo, Masaharu Kawano, Toshikazu Fukuda, Sachiko Kobayashi, Atsushi Kurokawa
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) 2016.5
-
Structure optimization for timing in nano scale FinFET
Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa
IEICE ELECTRONICS EXPRESS 12 ( 9 ) 2015.5
-
Structure optimization for timing in nano scale FinFET
Kanamoto Toshiki, Akamine Takeichiro, Ammo Hiroaki, Hasegawa Takashi, Shimizu Kouhei, Kumano Yoshinori, Kawano Masaharu, Kurokawa Atsushi
IEICE Electron. Express 12 ( 9 ) 20150297 - 20150297 2015.4
-
Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Kanamoto Toshiki, Inaba Hisato, Chiba Toshiharu, Ogasahara Yasuhiro
IEICE Electron. Express 11 ( 3 ) 20130813 - 20130813 2014.4
-
Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate
Toshiki Kanamoto, Hisato Inaba, Toshiharu Chiba, Yasuhiro Ogasahara
IEICE ELECTRONICS EXPRESS 11 ( 3 ) 2014
-
Supply Noise Suppression by Triple-Well Structure
Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 ( 4 ) 781 - 785 2013.4
-
Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
Takashi Saito, Akihiro Tanaka, Takuro Hayashi, Hideyuki Kikuchihara, Toshiki Kanamoto, Hiroo Masuda, Masataka Miyake, Shuhei Amakawa, Hans J. Mattausch, Michiko Miura-Mattausch
JAPANESE JOURNAL OF APPLIED PHYSICS 50 ( 4 ) 2011.4
-
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
Takashi Saito, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A ( 9 ) 1605 - 1611 2010.9
-
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 8 ) 1349 - 1358 2010.8
-
Impact of Self-Heating in Wire Interconnection on Timing
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
IEICE TRANSACTIONS ON ELECTRONICS E93C ( 3 ) 388 - 392 2010.3
-
Interconnect Modeling: A Physical Design Perspective
Atsushi Kurokawa, Takashi Sato, Toshiki Kanamoto, Masanori Hashimoto
IEEE TRANSACTIONS ON ELECTRON DEVICES 56 ( 9 ) 1840 - 1851 2009.9
-
An approach for reducing leakage current variation due to manufacturing variability
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3016 - 3023 2009
-
Improvement in computational accuracy of output transition time variation considering threshold voltage variations
Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 4 ) 990 - 997 2009
-
Impact of Well Edge Proximity Effect on Timing
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3461 - 3464 2008.12
-
A parallel method to extract critical areas of net pairs for diagnosing bridge faults
Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3524 - 3530 2008
-
Method of extracting pairs of adjacent wires for diagnosing bridging faults based on IDDQ testing
末光啓一, 伊藤俊明, 金本俊幾, 寺井正幸, 小谷憲, 澤田茂穂
情報処理学会シンポジウム論文集 2007 ( 7 ) 215 - 220 2007.8
-
A fast characterizing method for large embedded memory modules on SoC
Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E90A ( 4 ) 815 - 822 2007.4
-
Impact of intrinsic parasitic extraction errors on timing and noise estimation
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kbayashi, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3666 - 3670 2006.12
-
Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006.12