Papers - IMAI Masashi
-
Substrate contact effect on TSV-to-TSV coupling
Rosely Karel, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Atsushi Kurokaw
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A04 2014.8
-
Modeling and analysis of vertical interconnects in 3D ICs
Nanako Niioka, Masashi Imai, Masa-aki Fukase, Rosely Karel, Tetsuya Kobayashi, Atsushi Kurokawa
Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session) 1A03 2014.8
-
Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking Asynchronous Circuits
Masashi Imai, Tomohiro Yoneda
Proc. ISCAS2014 2014.6
-
The Frontline of Dependable VLSI Systems 2014
Masashi Imai
2014.6
-
High-Throughput Partially Parallel Inter-chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Tadahiro Hanyu
IEICE Trans on Inf.&Syst. E97-D ( 6 ) 1546 - 1556 2014.6
-
The Frontline of Dependable VLSI Systems 2014
Masashi Imai
WIT2014 2014.6
-
Construction of Design Environment for Asynchronous Circuits using DDL Cell Library
Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo
Technical Report of IEICE 3 - 8 2014.4
-
Scan test of MOUSETRAP pipeline circuit
Kyohei Terayama, Masashi Imai
49 - 49 2014.3
-
Modeling and Analysis of Vertical Interconnects in 3D ICs
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2014 ( 0 ) 3 - 3 2014
-
Substrate Contact Effect on TSV-to-TSV Coupling
Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan 2014 ( 0 ) 4 - 4 2014
-
Variability Evaluation and Characterization of Multi-clock Dual-Edge-Triggered FlipFlops
Masashi Imai, Tomohiro Yoneda
Proc. IEEE/ACM Workshop on Variability Modeling and Characterization 2013 2013.11
-
Proposal of Double-clock and Dual-Edge-Triggered Flip-Flops for Asynchronous Circuits
VLD2013 2013.10
-
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
Masashi Imai, Tomohiro Yoneda
IEICE Trans on Inf.&Syst. E96-D ( 9 ) 1914 - 1925 2013.9
-
Hetero-timing Circuit Design using Multi-Clock Dual-Edge-Triggered Flip-Flops
870 - 875 2013.9
-
High Performance Asynchronous Circuit Design using Multi-bit Storage Cells
864 - 869 2013.9
-
可変クロック方式の開発
小田桐舞央,今井雅,黒川敦,深瀬政秋
電気関係学会東北支部連合大会 1C04 2013.8
-
Development of a built-in clock circuit
2013.3
-
7.3 Asynchronous Networks-on-Chip(7. Responsiveness,<Special Survey>Dependable VLSI System)
YONEDA Tomohiro, IMAI Masashi
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 482 - 482 2013
-
10.5 Fault Detection and Reconfiguration Method for Multiple CPU Cores(10. Future and / or Un-Identified Problems,<Special Survey>Dependable VLSI System)
IMAI Masashi, YONEDA Tomohiro
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 514 - 514 2013
-
可変クロック方式の開発
小田桐 舞央, 今井 雅, 黒川 敦, 深瀬 政秋
電気関係学会東北支部連合大会講演論文集 2013 ( 0 ) 32 - 32 2013