Papers - IMAI Masashi
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A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura
IEICE Technical Report VLD2010-66 67 - 72 2010.10
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Hard-redundant Fault Tolerance Techniques for Resilient Protection Relay Systems
Tomoyuki Kawasaki, Katsuhiko Sekiguchi, Kazuto Fukushima, Takaya Shono, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. 16th International Conference on Electrical Engineering 2010.7
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Pair and Swap: An Approach to Graceful Degradation for Dependable Chip Multiprocessors
Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. WDSN10 119 - 124 2010.6
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An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
VLD2009 ( 51 ) 67 - 72 2009.12
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An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya
IEICE Technical Report VLD2009-51,DC2009-38 67 - 72 2009.12
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N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD09 125 - 130 2009.10
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N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD2009 125 - 130 2009.10
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Principles of Asynchronous Design Style
2009.7
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Achieving Degradation Tolerance in a Hardware Accelerator with Parallel Functional Units
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Atsushi Matsumoto
Proc. of Third Workshop on Dependable and Secure Nanocomputing 28 - 33 2009.6
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Fine-grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-Threshold-Voltage Transistors
Masashi Imai, Kouei Takada, Takashi Nanya
Proc. Async2009 209 - 216 2009.5
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Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
VLD2008 ( 90 ) 183 - 188 2008.11
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Performance Comparison between Self-timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors
Masashi Imai, Takashi Nanya
Proc. DSN08 2nd Workshop on Dependable and Secure Nanocomputing C23 - C28 2008.6
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A Method of Priority Control for Low-Power in Chip Multiprocessors
317 - 324 2008.6
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A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries
Masashi Imai, Takashi Nanya
Proc. ACSD08 21 - 26 2008.6
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共有資源の優先度制御によるチップ・マルチプロセッサの小電力化手法
椎名公康, 近藤正章, 今井雅, 中村宏, 南谷崇
先進的計算基盤システムシンポジウム SACSIS 2008 317 - 324 2008.6
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An approach to tolerating delay faults based on asynchronous circuits
2008.4
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An Approach to Tolerating Delay Faults based on Asynchronous Circuits
Tomohiro Yoneda, Masashi Imai, Atsushi Matsumoto, Takahiro Hanyu, Yuichi Nakamura
IEICE Technical Report 2008.4
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A Process-variation-aware low-power technique using current control
VLD2007 ( 76 ) 37 - 42 2007.11
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A Method of Priority and Voltage/Frequency Control for Low-Power in Chip Multiprocessors
ARC-175 83 - 88 2007.11
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A Plan of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs
ARC-173 79 - 84 2007.5