Papers - IMAI Masashi
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Principles of Asynchronous Design Style
2009.7
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Achieving Degradation Tolerance in a Hardware Accelerator with Parallel Functional Units
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Atsushi Matsumoto
Proc. of Third Workshop on Dependable and Secure Nanocomputing 28 - 33 2009.6
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Fine-grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-Threshold-Voltage Transistors
Masashi Imai, Kouei Takada, Takashi Nanya
Proc. Async2009 209 - 216 2009.5
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Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
VLD2008 ( 90 ) 183 - 188 2008.11
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Performance Comparison between Self-timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors
Masashi Imai, Takashi Nanya
Proc. DSN08 2nd Workshop on Dependable and Secure Nanocomputing C23 - C28 2008.6
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A Method of Priority Control for Low-Power in Chip Multiprocessors
317 - 324 2008.6
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A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries
Masashi Imai, Takashi Nanya
Proc. ACSD08 21 - 26 2008.6
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共有資源の優先度制御によるチップ・マルチプロセッサの小電力化手法
椎名公康, 近藤正章, 今井雅, 中村宏, 南谷崇
先進的計算基盤システムシンポジウム SACSIS 2008 317 - 324 2008.6
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An approach to tolerating delay faults based on asynchronous circuits
2008.4
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An Approach to Tolerating Delay Faults based on Asynchronous Circuits
Tomohiro Yoneda, Masashi Imai, Atsushi Matsumoto, Takahiro Hanyu, Yuichi Nakamura
IEICE Technical Report 2008.4
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A Process-variation-aware low-power technique using current control
VLD2007 ( 76 ) 37 - 42 2007.11
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A Method of Priority and Voltage/Frequency Control for Low-Power in Chip Multiprocessors
ARC-175 83 - 88 2007.11
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A Plan of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs
ARC-173 79 - 84 2007.5
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Design Method of High Performance and Low Power Functional Units Considering Delay Variations
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
IEICE Trans on Fundamentals E89-A ( 12 ) 3519 - 3528 2006.12
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A Novel Checkpointing for Cluster System with Non-uniform Failure-Rate
J89-D ( 8 ) 1705 - 1716 2006.8
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Overhead-Conscious Task Scheduling Scheme for Reducing Energy Consumption of Multi-Processor System-on-Chip
ARC-169 67 - 72 2006.8
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Low Power Delay-Insensitive Asynchronous Circuits using 1-out-of-4 Encoding
ICD2006 ( 82 ) 19 - 24 2006.8
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A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations
Masashi Imai, Takashi Nanya
Proc. Async2006 68 - 77 2006.3
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遅延変動特性を考慮したタイミング信号設計方式に関する検討
今井 雅,渡邊孝一,近藤正章,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2005 ( 59 ) 31 - 36 2005.11
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Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
VLD2005 ( 60 ) 37 - 42 2005.11