Papers - IMAI Masashi
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Evaluation of Delay Variation in Asynchronous Circuits based on the Scalable-Delay-Insensitive Model
Masashi Imai,Metehan Ozcan,Takashi Nanya
Proc. Async2004 62 - 71 2004.4
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Synthesis of serial local clock controllers for asynchronous circuit design
N.Sretasereekul, H.Saito, E.Kim, M.Imai, M.Ozcan, H.Nakamura, T.Nanya
IEICE Trans on Fundamentals E86-A12 3028 - 3037 2003.12
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Evaluation of Checkpointing Mechanism on SCore Cluster System
Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Atsushi Hori
IEICE Trans on Inf.&Syst., E86-D ( 12 ) 2553 - 2563 2003.12
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同期式仕様記述を用いた非同期式VLSI設計支援CADシステムの構築と評価
今井 雅,Metehan Ozcan,小暮千賀明,齋藤 寛,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 84 ) 85 - 90 2003.11
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非同期データパス合成における解探索空間の削減
川鍋昌紀,齋藤 寛,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 82 ) 73 - 78 2003.11
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セルコントローラに基づいた非同期式制御回路の合成
齋藤 寛,川鍋昌紀,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 83 ) 79 - 84 2003.11
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Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits
Metehan Ocan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Trans. of IPSJ 44 ( 5 ) 1244 - 1254 2003.5
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Control signal sharing using data-path delay information at control data flow graph description
H.Saito, E.Kim, N.Sretasereekul, M.Imai, H.Nakamura, T.Nanya
Proc. Async2003 184 - 193 2003.5
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Control signal sharing of asynchroonous circuits using datapath delay information
H.Saito, E.Kim. M.Imai, N.Sretasereekul, H.Nakamura, T.Nanya
Proc. ISCAS2003 617 - 620 2003.5
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A zero-time-overhead asynchronous four-phase controller
N.Sretasereekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nakamura, T.Nanya
Proc. ISCAS2003 205 - 208 2003.5
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Design and Evaluation of High Performance Microprocessor with Reconfigurable On-Chip Memory
Taku Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
Proc. APCCAS2002 211 - 216 2002.12
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Analysis on Checkpointing Mechanism of SCore Cluster System
T.Hayashida, M.Kondo, M.Imai, H.Nakamura, T.Nanya, and A.Hori
Fastabstract of IEEE PRDC02 1 - 2 2002.12
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Flexible Partitioning of CDFGs for Compact Asynchronous Controllers
Nattha Sretasereekul, Y. Okuyama, H. Saito, M. Imai, K. Kuroda, T. Nanya
Proc. International Technical Conference on Circuits/Systems, Computers and Communications 1724 - 1727 2002.7
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Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchrounous Data-Path Circuits
Metehan Ozcan, Masashi Imai, Takashi Nanya
Proc. Async2002 109 - 114 2002.4
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Prospect of a stanniocalcin endocrine/paracrine system in mammals.
Ishibashi K, Imai M
American journal of physiology. Renal physiology 282 ( 3 ) F367 - 75 2002.3
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遅延情報を利用した非同期式VLSI設計の一手法の提案
今井 雅,南谷 崇
電子情報通信学会技術研究報告 VLD2001 ( 120 ) 51 - 57 2001.11
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Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, Takashi Nanya
Proc. Async2001 162 - 172 2001.3
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A Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, Takashi Nanya
IEICE Trans. on Electronics E84-C ( 2 ) 229 - 237 2001.2
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遅延情報を利用した非同期式RTL設計モデルの提案
今井 雅,南谷 崇
電子情報通信学会技術研究報告 VLD2000 ( 92 ) 137 - 142 2000.11
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2線式ドミノ論理による細粒度パイプライン・データパスの性能比較
今井 雅,南谷 崇
電子情報通信学会技術研究報告 CPSY99 ( 93 ) 73 - 80 1999.11