Papers - IMAI Masashi
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Task and Voltage Scheduling for Reducing Energy Consumption on GALS System-on-Chip
ARC-164 61 - 66 2005.8
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Initial Discussion about Adaptive Checkpointing for HPC Cluster in View of Fluctuate of Failure-Rate
DC2005 ( 14 ) 7 - 12 2005.8
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A Novel Design Method using Delay-Variation-Aware Cell Libraries for Asynchronous Bundled-data Transfer Circuits
Masashi Imai, Chikaaki Kogure, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Proc. ITC-CSCC2005 441 - 442 2005.7
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Single Latched Scan Registers based on Multi-Clock for Low Heat Dissipation and for Low IR-Drop
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
Proc. ITC-CSCC2005 945 - 946 2005.7
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A Design Method for a Standard Cell Library Considering Delay Variation
VLD2004 ( 63 ) 13 - 18 2004.12
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Skewed Checkpointing for Tolerating Multi-Node Failures
Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
Proc. SRDS2004 116 - 125 2004.10
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Asynchronous scan-latch controller for low area overhead DFT
M.Tsukisaka, M.Imai, T.Nanya
Proc. ICCD2004 66 - 71 2004.10
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A Synthesis Method of Asynchronous Control Circuits from a Behaviroal Description
289 - 294 2004.7
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Skewed Checkpointing for Tolerating Multi-Node Failures in Cluster System
DC2004 ( 19 ) 37 - 42 2004.7
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Design Space Reduction Filter in Asynchronous Data-path Synthesis
295 - 300 2004.7
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Evaluation of Delay Variation in Asynchronous Circuits based on the Scalable-Delay-Insensitive Model
Masashi Imai,Metehan Ozcan,Takashi Nanya
Proc. Async2004 62 - 71 2004.4
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Synthesis of serial local clock controllers for asynchronous circuit design
N.Sretasereekul, H.Saito, E.Kim, M.Imai, M.Ozcan, H.Nakamura, T.Nanya
IEICE Trans on Fundamentals E86-A12 3028 - 3037 2003.12
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Evaluation of Checkpointing Mechanism on SCore Cluster System
Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Atsushi Hori
IEICE Trans on Inf.&Syst., E86-D ( 12 ) 2553 - 2563 2003.12
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同期式仕様記述を用いた非同期式VLSI設計支援CADシステムの構築と評価
今井 雅,Metehan Ozcan,小暮千賀明,齋藤 寛,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 84 ) 85 - 90 2003.11
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セルコントローラに基づいた非同期式制御回路の合成
齋藤 寛,川鍋昌紀,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 83 ) 79 - 84 2003.11
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非同期データパス合成における解探索空間の削減
川鍋昌紀,齋藤 寛,今井 雅,中村 宏,南谷 崇
電子情報通信学会技術研究報告 VLD2003 ( 82 ) 73 - 78 2003.11
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Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits
Metehan Ocan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Trans. of IPSJ 44 ( 5 ) 1244 - 1254 2003.5
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A zero-time-overhead asynchronous four-phase controller
N.Sretasereekul, H.Saito, M.Imai, E.Kim, M.Ozcan, K.Thongnoo, H.Nakamura, T.Nanya
Proc. ISCAS2003 205 - 208 2003.5
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Control signal sharing using data-path delay information at control data flow graph description
H.Saito, E.Kim, N.Sretasereekul, M.Imai, H.Nakamura, T.Nanya
Proc. Async2003 184 - 193 2003.5
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Control signal sharing of asynchroonous circuits using datapath delay information
H.Saito, E.Kim. M.Imai, N.Sretasereekul, H.Nakamura, T.Nanya
Proc. ISCAS2003 617 - 620 2003.5