Papers - IMAI Masashi
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Performance Modeling and Analysis of On-chip Networks for Real-time Applications
Masashi Imai, Tomohiro Yoneda
Proc. of PRDC2012 111 - 120 2012.11
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Multi-Chip NoCs for Automotive Applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proc. PRDC2012 105 - 110 2012.11
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Floorplan Method for SDI-model-based Asynchronous Circuits to Achieve High Robustness against Delay Variations
Masashi Imai, Tomohiro Yoneda
IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems 2012 2012.11
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Dependable Routing in Multi-Chip NoC Platforms for Automotive Applications
Tomohiro Yoneda, Masashi Imai
Proc. DFT2012 217 - 224 2012.10
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A Study of Placed-and-Routed Design Method for High-Performance Asynchronous Circuits Considering Delay Constraints
1137 - 1142 2012.9
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Multi-chip NoCs for automotive applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 105 - 110 2012
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Performance modeling and analysis of on-chip networks for real-time applications
Masashi Imai, Tomohiro Yoneda
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 111 - 120 2012
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Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
Masashi Imai, Tomohiro Yoneda
Proc. DFT2011 463 - 471 2011.10
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Improrving Dependability and Performance of Fully Asynchronous On-chip Networks
Masashi Imai, Tomohiro Yoneda
Proc. Async2011 65 - 76 2011.4
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An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors
James Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. PRDC2010 62 - 69 2010.12
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A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
VLD2010 ( 66 ) 67 - 72 2010.11
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DSN2010 Report
DC2010 ( 23 ) 31 - 34 2010.10
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Evaluation of Delay Variations and Soft-Error Hardness in Asynchronous Pipeline Circuits
Masashi Imai, Tomohiro Yoneda
Proc. IEEE/ACM Workshop on Variability Modeling and Characterization 2010.10
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A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura
IEICE Technical Report VLD2010-66 67 - 72 2010.10
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Hard-redundant Fault Tolerance Techniques for Resilient Protection Relay Systems
Tomoyuki Kawasaki, Katsuhiko Sekiguchi, Kazuto Fukushima, Takaya Shono, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. 16th International Conference on Electrical Engineering 2010.7
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Pair and Swap: An Approach to Graceful Degradation for Dependable Chip Multiprocessors
Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. WDSN10 119 - 124 2010.6
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An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
VLD2009 ( 51 ) 67 - 72 2009.12
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An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya
IEICE Technical Report VLD2009-51,DC2009-38 67 - 72 2009.12
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N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD09 125 - 130 2009.10
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N-way Ring and Square Arbiters
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
Proc. ICCD2009 125 - 130 2009.10