Papers - IMAI Masashi
-
Hetero-timing Circuit Design using Multi-Clock Dual-Edge-Triggered Flip-Flops
870 - 875 2013.9
-
High Performance Asynchronous Circuit Design using Multi-bit Storage Cells
864 - 869 2013.9
-
可変クロック方式の開発
小田桐舞央,今井雅,黒川敦,深瀬政秋
電気関係学会東北支部連合大会 1C04 2013.8
-
Development of a built-in clock circuit
2013.3
-
可変クロック方式の開発
小田桐 舞央, 今井 雅, 黒川 敦, 深瀬 政秋
電気関係学会東北支部連合大会講演論文集 2013 ( 0 ) 32 - 32 2013
-
7.3 Asynchronous Networks-on-Chip(7. Responsiveness,<Special Survey>Dependable VLSI System)
YONEDA Tomohiro, IMAI Masashi
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 482 - 482 2013
-
10.5 Fault Detection and Reconfiguration Method for Multiple CPU Cores(10. Future and / or Un-Identified Problems,<Special Survey>Dependable VLSI System)
IMAI Masashi, YONEDA Tomohiro
The Journal of Reliability Engineering Association of Japan 35 ( 8 ) 514 - 514 2013
-
Performance Modeling and Analysis of On-chip Networks for Real-time Applications
Masashi Imai, Tomohiro Yoneda
Proc. of PRDC2012 111 - 120 2012.11
-
Multi-Chip NoCs for Automotive Applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proc. PRDC2012 105 - 110 2012.11
-
Floorplan Method for SDI-model-based Asynchronous Circuits to Achieve High Robustness against Delay Variations
Masashi Imai, Tomohiro Yoneda
IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems 2012 2012.11
-
Dependable Routing in Multi-Chip NoC Platforms for Automotive Applications
Tomohiro Yoneda, Masashi Imai
Proc. DFT2012 217 - 224 2012.10
-
A Study of Placed-and-Routed Design Method for High-Performance Asynchronous Circuits Considering Delay Constraints
1137 - 1142 2012.9
-
Performance modeling and analysis of on-chip networks for real-time applications
Masashi Imai, Tomohiro Yoneda
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 111 - 120 2012
-
Multi-chip NoCs for automotive applications
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 105 - 110 2012
-
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
Masashi Imai, Tomohiro Yoneda
Proc. DFT2011 463 - 471 2011.10
-
Improrving Dependability and Performance of Fully Asynchronous On-chip Networks
Masashi Imai, Tomohiro Yoneda
Proc. Async2011 65 - 76 2011.4
-
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors
James Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
Proc. PRDC2010 62 - 69 2010.12
-
A Study of High-Performance Asynchronous Network-on-Chip Focused on Bias of Packets Transfer Routes
VLD2010 ( 66 ) 67 - 72 2010.11
-
DSN2010 Report
DC2010 ( 23 ) 31 - 34 2010.10
-
Evaluation of Delay Variations and Soft-Error Hardness in Asynchronous Pipeline Circuits
Masashi Imai, Tomohiro Yoneda
Proc. IEEE/ACM Workshop on Variability Modeling and Characterization 2010.10