Papers - IMAI Masashi
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A Study on Low Power Sensor Node Communication using LoRa
Kan Hatakeyama, Sumio Tanba, Atsuhi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2020.2
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A Study on Equivalent Circuit Modeling of IGBT Towards Coupled Electro Thermal Stress Analysis for Power Module
Sota Ito, Tsuneo Munakata, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report, 2020.2
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Simulation-based On-chip Capacitance Extraction Method
Koki Kasai, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto
IPSJ Tohoku Branch SIG Technical Report 2020.2
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LPWA通信規格LoRaを用いたセンサノードの低消費電力通信の評価
畠山寛, 丹波澄雄, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-2 ) 2020.2
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メンテナンスフリーセンサノード実現に向けた画像分析と消費電力低減の検討
畑瀬拓実, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-3 ) 2020.2
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パワーモジュールの熱応力連成解析に向けたIGBT等価回路モデルに関する検討
伊藤颯汰, 宗形恒夫, 黒川敦, 今井雅, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 2-1 ) 2020.2
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シミュレーションベースオンチップ電源容量抽出手法
葛西孝己, 今井雅, 黒川敦, 金本俊幾
情報処理学会東北支部研究報告 2019-6 ( 1-1 ) 2020.2
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Quantitative Performance Comparison of Asynchronous and Synchronous Comparators
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2019 296 - 297 2019.10
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Efficiency Investigation of Capacitors Mounted on Re-distribution Layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
Proc. SASIMI2019 176 - 179 2019.10
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Thermal Modeling and Simulation of a Smart Wrist-worn Wearable Device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. SASIMI2019 138 - 143 2019.10
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Efficiency Investigation of Capacitors Mounted on Re-distribution Layers for FOWLP
Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto
Proc. SASIMI2019 176 - 179 2019.10
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Thermal Modeling and Simulation of a Smart Wrist-worn Wearable Device
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
Proc. SASIMI2019 138 - 143 2019.10
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Quantitative Performance Comparison of Asynchronous and Synchronous Comparators
Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Proc. SASIMI2019 296 - 297 2019.10
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A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
Proc. MWSCAS2019 1085 - 1088 2019.8
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A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
Proc. MWSCAS2019 1085 - 1088 2019.8
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Hardware Trojan Insertion and Detection in Asynchronous Circuits
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto
Proc.ASYNC2019 134 - 143 2019.5
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ASYNC2019
Masashi Imai
Proc. ASYNC2019 2019.5
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湘南会議No.133
Masashi Imai
湘南会議No.133報告 2019.5
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Neural network-based 3D IC interconnect capacitance extraction
Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa
Proc. ICCET2019 168 - 172 2019.4
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Neural network-based 3D IC interconnect capacitance extraction
Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa
PROCEEDINGS OF 2019 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION ENGINEERING AND TECHNOLOGY (ICCET 2019) 168 - 172 2019.4